Closed-form analytical model of static noise margin for ultra-low voltage eight-transistor tunnel FET static random access memory

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A tunnel FET (TFET) is a candidate replacement for conventional MOSFETs to realize low-power LSI. The most significant issue with the practical application of TFETs concerns their low tunneling current. Si is an indirect-gap material with a low band-to-band tunneling probability and is not favored for the channel. However, a new technology has recently been proposed to enhance the tunneling current in Si-TFETs by utilizing isoelectronic trap (IET) technology. IET technology provides an innovative approach to realizing low-power LSI with TFETs. In this paper, state-ofthe-art research on Si-TFETs with IET technology from the viewpoint of process and device integration is reviewed.

Section: Variabilitymentioning

confidence: 99%

Process and device integration for silicon tunnel FETs utilizing isoelectronic trap technology to enhance the ON current

Mori

Asai

Fukuda

et al. 2018

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“…For example, Fuketa et al discussed the impact of the variability in TFET-based static random access memories (SRAMs). 25) They reported that a maximum V th variation of less than 15 and 10 mV is required for 0.4 and 0.3 V operation, respectively, in order to realize small read failure probabilities P RF less than 10 −6 . Therefore, it is critical to suppress the variability in order to achieve TFET-based circuits that have a low power consumption.…”

Section: Introductionmentioning

confidence: 99%

Suppression of tunneling rate fluctuations in tunnel field-effect transistors by enhancing tunneling probability

Mori¹,

Migita²,

Fukuda³

et al. 2017

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This paper discusses the impact of the tunneling probability on the variability of tunnel field-effect transistors (TFETs). Isoelectronic trap (IET) technology, which enhances the tunneling current in TFETs, is used to suppress the variability of the ON current and threshold voltage. The simulation results show that suppressing the tunneling rate fluctuations results in suppression of the variability. In addition, a formula describing the relationship between the tunneling rate fluctuations and the electric field strength is derived based on Kane's band-to-band tunneling model. This formula indicates that the magnitude of the tunneling rate fluctuations is proportional to the magnitude of the fluctuations in the electric field strength and a higher tunneling probability results in a lower variability. The derived relationship is universally valid for any technologies that exploit enhancement of the tunneling probability, including IET technology, channel material engineering, heterojunctions, strain engineering, etc.

“…Tunnel field-effect transistors (TFETs) are widely studied as candidates for low-power applications beyond complementary metal-oxide-semiconductor (CMOS) technologies. [1][2][3][4][5][6][7] Although many successfully fabricated TFET devices are reported in the literature, the basic characteristics of TFETs are still unclear as compared with metal-oxide-semiconductor field-effect-transistors (MOSFETs). Among the various features of semiconductor transistors, the most important one is scalability.…”

Section: Introductionmentioning

confidence: 99%

On the drain bias dependence of long-channel silicon-on-insulator-based tunnel field-effect transistors

Fukuda

Mori

Asai

et al. 2017

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The drain bias dependence of tunnel field-effect transistors (TFETs) is examined on the basis of the measured characteristics and device simulation to understand the electrical behavior of TFETs. Our analyses focus on the long-channel silicon-on-insulator (SOI)-based TFETs as a good basis for further studies of short-channel effects, scaling issues, and more complicated device structures, such as multigate or nanowire TFETs. By device simulation, it is revealed that the drain bias dependence of the transfer characteristics of the measured TFETs is governed by two physical mechanisms: the density of states (DOS) occupancy factor, which depends on drain-to-source bias voltage, and channel electrostatic potential, which is limited by the drain bias through strong carrier accumulation. These mechanisms differ from the drain-induced barrier lowering (DIBL) of metal–oxide–semiconductor field-effect-transistors (MOSFETs), and cause a significant impact even in long-channel SOIs. Finally, the obtained insights are successfully implemented in a TFET compact model.