Closed-Form Expressions for Extending Step Delay and Slew Metrics to Ramp Inputs for RC Trees

Kashyap, Chandramouli; Alpert, Charles J.; Liu, F.; Devgan, Anirudh

doi:10.1109/tcad.2004.825861

Cited by 53 publications

(36 citation statements)

References 7 publications

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“…We now describe the structure and modeling assumptions used in our STA algorithm (the core timer inside the Monte Carlo loops) and gate library. The STA computes signal delays at all the circuit nodes, using the Elmore delay metric [19] for wire delay, the PERI technique [20] with the Bakoglu metric [21] for wire slew, and rank-one quadratic functions [22] to model gate delay and gate output slew. The gate output slew and gate delay are modeled as functions of the input slew and 4 statistical parameters: L, W , V t and t ox .…”

Section: Methodsmentioning

confidence: 99%

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Exploiting correlation kernels for efficient handling of intra-die spatial correlation, with application to statistical timing

Singhee

Singhal

Rutenbar

2008

Proceedings of the Conference on Design, Automation and Test in Europe

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Intra-die manufacturing variations are unavoidable in nanoscale processes. These variations often exhibit strong spatial correlation. Standard grid-based models assume model parameters (grid-size, regularity) in an ad hoc manner and can have high measurement cost [1]. The random field model [1][2] overcomes these issues. However, no general algorithm has been proposed for the practical use of this model in statistical CAD tools. In this paper, we propose a robust and efficient numerical method, based on the Galerkin technique [3] and Karhunen Loéve Expansion [4], that enables effective use of the model. We test the effectiveness of the technique using a Monte Carlo-based Statistical Static Timing Analysis algorithm, and see errors less than 2 8%, while reducing the number of random variables from thousands to 25, resulting in speedups of up to 10x.

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Section: Methodsmentioning

confidence: 99%

“…We approximate g´xµ by its value at the centroid x of . Then we can write I Î g´x µdx g´x µa (20) Hence, the double integral in (18) is approximated by…”

Section: Numerical Integrationmentioning

confidence: 99%

Exploiting correlation kernels for efficient handling of intra-die spatial correlation, with application to statistical timing

Singhee

Singhal

Rutenbar

2008

Proceedings of the Conference on Design, Automation and Test in Europe

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“…There is a large literature on Elmore delay and related topics; see, e.g., Alpert et al (2001a), Kashyap et al (2004), Kahng and Muddu (1997), Gupta et al (1997), Schevon (1995), andHorowitz (1984). Rubenstein et al (1983) published the simple closed-form formula described above for computing the mean of the impulse response of RC interconnect trees.…”

Section: Rc Tree Optimizationmentioning

confidence: 99%

“…The square root of the second central moment, i.e., the standard deviation i of the associated random variable, has a natural interpretation as the transition time or rise time of the signal at node i; see, e.g., Kashyap et al (2004) and Lin and Pileggi (2001).…”

Section: Rc Tree Optimizationmentioning

confidence: 99%

Digital Circuit Optimization via Geometric Programming

Boyd

Kim

Patil

et al. 2005

Operations Research

154

146

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This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistor-capacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.

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“…It also makes the analysis of cascaded stages much simpler (such as optimal repeater insertion, as discussed later in section 8.5, as the delay of one driver plus interconnect stage is assumed independent of the waveform of the previous stage. In those cases where the approximation is not accurate enough, one can use more complex models that take finite rise-times into account [47][48][49][50].…”

Section: Classical Delay Modelsmentioning

confidence: 99%

On-chip data communication : analysis, optimization and circuit design

Schinkel¹

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Closed-Form Expressions for Extending Step Delay and Slew Metrics to Ramp Inputs for RC Trees

Cited by 53 publications

References 7 publications

Exploiting correlation kernels for efficient handling of intra-die spatial correlation, with application to statistical timing

Exploiting correlation kernels for efficient handling of intra-die spatial correlation, with application to statistical timing

Digital Circuit Optimization via Geometric Programming

On-chip data communication : analysis, optimization and circuit design

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