Closing the gap between hardware and software: hardware-software cosynthesis at Oxford

Page, Ian

doi:10.1049/ic:19960221

Cited by 10 publications

(6 citation statements)

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“…Originally developed in the Hardware Compilation Research Group at Oxford University [31], it was commercialised by Celoxica, and is now provided by Mentor Graphics [30]. Handel-C extends ANSI C with constructs that address the issues identified in the previous paragraph.…”

Section: Implementing Machine Vision Systems Using Fpgasmentioning

confidence: 99%

Implementing Machine Vision Systems Using FPGAs

Bailey¹

2012

Machine Vision Handbook

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Section: Implementing Machine Vision Systems Using Fpgasmentioning

confidence: 99%

Implementing Machine Vision Systems Using FPGAs

Bailey¹

2012

Machine Vision Handbook

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“…There are many academic and commercial compilers that are based on synthesis to generate a customized circuit for a given task. Examples of such compilers include Impulse Accelerated Technologies Impulse C [13], Altera's C2H [2], Trident [3], Mitrionics Mitrion-C [1], SRC Computer's SRC Carte, ASC [14], and Celoxica's Handel-C [15]. Typically, these tools will compile C-like code to circuit descriptions in HDL which can then be synthesized by standard FPGA International Journal of Reconfigurable Computing 3 CAD tools for deployment on accelerator systems such as the Xtremedata XD1000.…”

Section: Behavioral Synthesis-based Compilersmentioning

confidence: 99%

The Potential for a GPU-Like Overlay Architecture for FPGAs

Kingyens¹,

Steffan

2011

International Journal of Reconfigurable Computing

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We propose a soft processor programming model and architecture inspired by graphics processing units (GPUs) that are well-matched to the strengths of FPGAs, namely, highly parallel and pipelinable computation. In particular, our soft processor architecture exploits multithreading, vector operations, and predication to supply a floating-point pipeline of 64 stages via hardware support for up to 256 concurrent thread contexts. The key new contributions of our architecture are mechanisms for managing threads and register files that maximize data-level and instruction-level parallelism while overcoming the challenges of port limitations of FPGA block memories as well as memory and pipeline latency. Through simulation of a system that (i) is programmable via NVIDIA's high-levelCglanguage, (ii) supports AMD's CTM r5xx GPU ISA, and (iii) is realizable on an XtremeData XD1000 FPGA-based accelerator system, we demonstrate the potential for such a system to achieve 100% utilization of a deeply pipelined floating-point datapath.

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“…The lack of a central management scheme that manages and coordinates among concurrent users and applications on a running RC system. The need for a high level design language and methodology for RC is a well acknowledged issue that have drawn numerous research interests [4,5,6]. In this paper, we present BORPH, the Berkeley Operating system for ReProgrammable Hardware.…”

Section: Introductionmentioning

confidence: 99%

Improving Usability of FPGA-Based Reconfigurable Computers Through Operating System Support

Brodersen

2006

2006 International Conference on Field Programmable Logic and Applications

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Advances in FPGA-based reconfigurable computers have made them a viable computing platform for a vast variety of computation demanding areas such as bioinformatics, speech recognition, and high-end digital signal processing. The lack of common, intuitive operating system support, however, hinders their wide deployment. This paper presents BORPH, an operating system framework for FPGA-based reconfigurable computers with a goal to ease and accelerate development of high-level applications to run on these computers. It provides kernel support for FPGA resources by extending a standard Linux operating system. Users therefore compile and execute hardware processes on FPGA resources the same way they run software processes on conventional processor-based systems. The operating system offers run-time general file system support to hardware processes as if they were software. Furthermore, a virtual file system is built to allow access to memories and registers defined in the FPGA, which provides communication links with running hardware processes. Increased productivities have been observed for high-level application developers, who have few previous experiences in hardware design, to implement complex mixed software/ hardware designs on a FPGA-based reconfigurable computer running BORPH.

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Closing the gap between hardware and software: hardware-software cosynthesis at Oxford

Cited by 10 publications

References 0 publications

Implementing Machine Vision Systems Using FPGAs

Implementing Machine Vision Systems Using FPGAs

The Potential for a GPU-Like Overlay Architecture for FPGAs

Improving Usability of FPGA-Based Reconfigurable Computers Through Operating System Support

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