Clustered Fault Tolerance TSV Planning for 3-D Integrated Circuits

Xu, Qi; Chen, Song; Xu, Xia; Yu, Bei

doi:10.1109/tcad.2017.2681080

Cited by 28 publications

(41 citation statements)

References 32 publications

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“…To calculate the size of switches, we introduce two types of binary variables x i, j,k uv and d uv . x i, j,k uv = 1 indicates that the (k + 1)-th routing path of the communication flow (i, j) goes through the edge (u, v) ∈ E pa , 0 ≤ k ≤ K; otherwise, x i, j,k uv = 0. d uv = 1 indicates that there is at least one communication flow going through the edge (u, v) ∈ E pa , and accordingly a physical link exists between the switches u and v; otherwise, d uv = 0. d uv is calculated based on binary variables x i, j,k uv as follows [39].…”

Section: ) Computation Of Switch Power and Link Powermentioning

confidence: 99%

Generalized Fault-Tolerance Topology Generation for Application-Specific Network-on-Chips

Chen

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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The Network-on-Chips based communication architecture is a promising candidate for addressing communication bottlenecks in many-core processors and neural network processors. In this work, we consider the generalized fault-tolerance topology generation problem, where the link (physical channel) or switch failures can happen, for application-specific network-onchips (ASNoC). With a user-defined maximum number of faults, K, we propose an integer linear programming (ILP) based method to generate ASNoC topologies, which can tolerate at most K faults in switches or links. Given the communication requirements between cores and their floorplan, we first propose a convexcost flow based method to solve a core mapping problem for building connections between the cores and switches. Second, an ILP based method is proposed to solve the routing path allocation problem, where K + 1 switch-disjoint routing paths are allocated for every communication flow between the cores. Finally, to reduce switch sizes, we propose sharing the switch ports for the connections between the cores and switches and formulate the port sharing problem as a clique-partitioning problem, which is solved by iteratively finding the maximum cliques. Additionally, we propose an ILP-based method to simultaneously solve the core mapping and routing path allocation problems when only physical link failures are considered. Experimental results show that the power consumptions of fault-tolerance topologies increase almost linearly with K because of the routing path redundancy for fault tolerance. When both switch faults and link faults are considered, port sharing can reduce the average power consumption of faulttolerance topologies with K = 1, K = 2 and K = 3 by 18.08%, 28.88%, and 34.20%, respectively. When considering only the physical link faults, the experimental results show that compared to the FTTG (fault-tolerant topology generation) algorithm, the proposed method reduces power consumption and hop count by 10.58% and 6.25%, respectively; compared to the DBG (de Bruijn Digraph) based method, the proposed method reduces power consumption and hop count by 21.72% and 9.35%, respectively.

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Section: ) Computation Of Switch Power and Link Powermentioning

confidence: 99%

Generalized Fault-Tolerance Topology Generation for Application-Specific Network-on-Chips

Chen

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…First, an integer programming formulation in [14] is given to generate the fault-tolerance structures with minimization of the multiplexer delay overhead.…”

Section: Integer Linear Programming Formulationmentioning

confidence: 99%

“…Though the integer programming method in [14] can generate K fault-tolerance structures using K s-TSVs, the method cannot be directly applied for the generation of adaptive faulttolerance structures, where the number of s-TSVs might be larger than K in K fault-tolerance structures. Then a new integer programming formulation is proposed to generate adaptive fault-tolerance structures in minimizing both the used s-TSV number and the multiplexer delay overhead.…”

Section: Integer Linear Programming Formulationmentioning

confidence: 99%

“…The generation of fault-tolerance structure is not considered since they assume regular struc-tures always exist. In [14], the TSV planning framework includes a top-down partitioning followed by a bottom-up iterative merging (clustering) for reducing the number of f-TSV groups. Then, a min-cost-max-flow based method is used to allocate s-TSVs for each group and an ILP model is adopted to generate fault-tolerance structures.…”

Section: Fault Tolerance Tsv Planningmentioning

confidence: 99%

“…Then, a min-cost-max-flow based method is used to allocate s-TSVs for each group and an ILP model is adopted to generate fault-tolerance structures. The same number of s-TSVs are allocated to all the f-TSV groups in [13], [14] and, for an f-TSV group, the key point is to ensure enough number of candidate s-TSVs that can be shared by all the f-TSVs in the group. As a result, many small f-TSV groups are formed, which potentially causes an overuse of s-TSVs.…”

Section: Fault Tolerance Tsv Planningmentioning

confidence: 99%

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Adaptive 3D-IC TSV Fault Tolerance Structure Generation

Chen

2019

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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In three dimensional integrated circuits (3D-ICs), through silicon via (TSV) is a critical technique in providing vertical connections. However, the yield and reliability is one of the key obstacles to adopt the TSV based 3D-ICs technology in industry. Various fault-tolerance structures using spare TSVs to repair faulty functional TSVs have been proposed in literature for yield and reliability enhancement, but a valid structure cannot always be found due to the lack of effective generation methods for fault-tolerance structures. In this paper, we focus on the problem of adaptive fault-tolerance structure generation. Given the relations between functional TSVs and spare TSVs, we first calculate the maximum number of tolerant faults in each TSV group. Then we propose an integer linear programming (ILP) based model to construct adaptive fault-tolerance structure with minimal multiplexer delay overhead and hardware cost. We further develop a speed-up technique through efficient min-cost-max-flow (MCMF) model. All the proposed methodologies are embedded in a top-down TSV planning framework to form functional TSV groups and generate adaptive faulttolerance structures. Experimental results show that, compared with state-of-the-art, the number of spare TSVs used for fault tolerance can be effectively reduced.Index Terms-3D-IC, fault-tolerance, TSV planning, TSV yield.

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Shallow trench isolation structure design for through‐silicon vias stress reduction

Wang

Liu

Yin

et al. 2022

Int J Numerical Modelling

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Through-silicon vias (TSVs) technology provides an effective approach for "more than Moore," however, the stress caused by TSVs may cause the surrounding devices to be squeezed and cause failure. In order to reduce the thermal stress of the TSV while innovatively considering the anisotropy of the silicon substrate, a shallow trench isolation (STI) structure was designed, and the influence of the shape and size of the STI on the stress reduction effect was studied. The research results show that the petal-shaped STI structure reduces the thermal stress caused by TSV by 26% and the KOZ area by 31%, which provides a solution for reducing the stress and KOZ area in the anisotropic silicon substrate.

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Clustered Fault Tolerance TSV Planning for 3-D Integrated Circuits

Cited by 28 publications

References 32 publications

Generalized Fault-Tolerance Topology Generation for Application-Specific Network-on-Chips

Generalized Fault-Tolerance Topology Generation for Application-Specific Network-on-Chips

Adaptive 3D-IC TSV Fault Tolerance Structure Generation

Shallow trench isolation structure design for through‐silicon vias stress reduction

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