Clustering techniques for coarse-grained, antifuse FPGAs

Kang, Chang Woo; Pedram, Massoud

doi:10.1145/1120725.1121017

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2006

2007

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Cited by 2 publications

(2 citation statements)

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“…In particular, the authors of [10] presented an area-driven clustering algorithm. They set up a pair of linear equations and calculated the minimum number of required pASIC3 logic cells.…”

Section: Introductionmentioning

confidence: 99%

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Low-power clustering with minimum logic replication for coarse-grained, antifuse based FPGAs

Kang

Pedram

2006

Proceedings of the 16th ACM Great Lakes Symposium on VLSI

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This paper presents a minimum area, low-power driven clustering algorithm for coarse-grained, antifuse-based FPGAs under delay constraints. The algorithm accurately predicts logic replication caused by timing constraint during the low-power driven clustering. This technique reduces size of duplicated logic substantially, resulting in benefits in area, delay, and power dissipation. First, we build power-delay curves at nodes with the aid of the prediction algorithm. Next, we choose the best cluster starting from primary outputs moving backward in the circuit based on these curves. Experimental results show 16% and 20% reduction in dynamic and leakage power dissipation with 18% area reduction compared to the results of clustering without the replication prediction.

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“…In particular, the authors of [10] presented an area-driven clustering algorithm. They set up a pair of linear equations and calculated the minimum number of required pASIC3 logic cells.…”

Section: Introductionmentioning

confidence: 99%

“…In this research, we follow the same flow as that in [10]. There are four different programmable gate groups (cf.…”

Section: Introductionmentioning

confidence: 99%