CMOS analog four-quadrant multiplier free of voltage reference generators

Sousa, Antonio Jose Sobrinho de; Andrade, Fabian de; Santos, Hildeloi dos; Goncalves, Gabriele Costa; Pereira, Maicon Deivid; Santana, Edson Pinto; Cunha, Ana Isabela Araújo

doi:10.1145/3338852.3339870

Cited by 5 publications

(6 citation statements)

References 13 publications

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“…This cancellation scheme differs from that of our previous work [18] by the two current sources here added and because the current subtractor of [18] is composed by three conventional cascode current mirrors.…”

Section: E Cancellation Schemementioning

confidence: 85%

“…Let us name vin1 and vin2 the bipolar voltage signals to be multiplied. According to (2.b), by setting vG1 = (vin1 + vin2) +VC1 and vG2 = (vin2 -vin1) +VC2, with  being a dimensionless constant and VC1,2 being constant voltages, then the current difference includes a term proportional to the product vin1vin2: In [18] we have presented a new method to apply the sum and the difference of the input signals vin1 and vin2 to the entries of the type VII basic cell of Fig. 1, without using inverters, amplifiers or reference voltages other than the supply voltages.…”

Section: Proposed Multiplier Architecturementioning

confidence: 99%

“…The accuracy of the joint operation of the arithmetic averaging and half-difference blocks depends upon the reliability of the before mentioned approximation: n 4  n 3  n. As a matter of fact, in most fabrication technologies the slope factor is between 1.0 and 1.4 and thus this approximation may be often unacceptable. As an improvement to the multiplier architecture first proposed by us in [18] and described in the previous Sections, the impact of non-unity slope factor over the distortion level can be mitigated by purposely imposing a geometric asymmetry between transistors M1 and M2 of each core. Assuming now that the aspect ratios of M1 and M2 are no longer equal, (2.a) is rewritten as: (11.a), leads to:…”

Section: Design Considerationsmentioning

confidence: 99%

“…In this work, a CMOS analog multiplier with two voltagemode inputs and a current-mode output is proposed and analyzed through simulation. This multiplier comprises a new method to apply voltage signals to the inputs of a singlequadrant multiplier, which avoids the use of voltage reference generators [18]. Four-quadrant multiplication is accomplished through a cancellation scheme over the output currents of four single-quadrant multipliers.…”

Section: Introductionmentioning

confidence: 99%

“…Four-quadrant multiplication is accomplished through a cancellation scheme over the output currents of four single-quadrant multipliers. The circuit presented and analyzed in our previous work [18] has been improved by the use of an asymmetric core and of a different current subtractor topology. The whole multiplier architecture and the dimensions of the devices correspond to the implementation of an integrated circuit in CMOS 130 nm technology.…”

Section: Introductionmentioning

confidence: 99%

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Compact CMOS Analog Multiplier Free of Voltage Reference Generators

Sousa

Andrade

Bomfim

et al. 2020

JICS

Self Cite

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This work presents a CMOS four quadrant analog multiplier architecture for application as the synapse element in analog cellular neural networks. For this reason, the circuit has voltage-mode inputs and a current-mode output and the chief design targets are compactness and low energy consumption. A signal application method is proposed that avoids voltage reference generators, which contributes to reduce sensitivity to supply voltage variation. Performance analysis through simulation has been accomplished for a design in CMOS 130 nm technology with 163 µm2 total active area. The circuit features ±50 mV input voltage range, 86 µW static power and ‑28.4 dB maximum total harmonic distortion. A simple technique for manual calibration is also presented.

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Section: E Cancellation Schemementioning

confidence: 85%

Section: Proposed Multiplier Architecturementioning

confidence: 99%

Section: Design Considerationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Compact CMOS Analog Multiplier Free of Voltage Reference Generators

Sousa

Andrade

Bomfim

et al. 2020

JICS

Self Cite

View full text Add to dashboard Cite

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A class AB ultra-low-power asymmetrical structured current multiplier

Mahmoodi,

Abrishamifar

2024

AEU - International Journal of Electronics and Communications

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CMOS Analog Simulators of Dynamical Systems

Araújo,

Oliveira,

Guerreiro

et al. 2024

IEEE Access

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Analog computing is based upon using physical processes to solve formal mathematical problems. In the past, it was the predominant instrument of scientific calculations. Now, as the physical limits imposed on digital devices compel research into alternate computing paradigms, a reexamination of the potentialities of analog computing is warranted. This work studies the application of analog CMOS cells toward the simulation of dynamical systems, and, more generally, solving sets of coupled time-dependent ordinary differential equations. Following a brief review of the fundamentals of systems theory and analog computing, the main set of computing elements is introduced, each comprising analog cells designed in a 130 nm process. These are subsequently applied to the realization of practical, special-purpose analog computing modules. Illustrative systems from various fields are selected for simulation. Though by no means comprehensive, these case studies highlight the capabilities of contemporary analog computing, especially in solving nonlinear problems. Circuit simulations show good agreement with solutions obtained from highorder numerical methods, at least over a limited range of system parameters. The article concludes with a brief discussion of broader analog computing applications, offering future prospects toward further exploration of its potentialities and limitations in a wide range of domains.INDEX TERMS Analog computers, differential equations, dynamical systems, integrated circuits.

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CMOS analog four-quadrant multiplier free of voltage reference generators

Cited by 5 publications

References 13 publications

Compact CMOS Analog Multiplier Free of Voltage Reference Generators

Compact CMOS Analog Multiplier Free of Voltage Reference Generators

A class AB ultra-low-power asymmetrical structured current multiplier

CMOS Analog Simulators of Dynamical Systems

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