2022
DOI: 10.48550/arxiv.2204.04430
|View full text |Cite
Preprint
|
Sign up to set email alerts
|

CMOS Circuit Implementation of Spiking Neural Network for Pattern Recognition Using On-chip Unsupervised STDP Learning

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1

Citation Types

0
3
0

Year Published

2023
2023
2025
2025

Publication Types

Select...
1
1

Relationship

0
2

Authors

Journals

citations
Cited by 2 publications
(3 citation statements)
references
References 0 publications
0
3
0
Order By: Relevance
“…For the chosen synaptic current, eNeuron3 has the fewest spikes in time compared to the other eNeurons [10], which results in the highest σ J over spike occurrences. Despite the four types of eNeurons described in the literature and used for STDP learning [6], [14], the obtained values for σ J are either of the same order of magnitude or exceed ∆T s .…”
Section: B Period Jittermentioning
confidence: 80%
See 2 more Smart Citations
“…For the chosen synaptic current, eNeuron3 has the fewest spikes in time compared to the other eNeurons [10], which results in the highest σ J over spike occurrences. Despite the four types of eNeurons described in the literature and used for STDP learning [6], [14], the obtained values for σ J are either of the same order of magnitude or exceed ∆T s .…”
Section: B Period Jittermentioning
confidence: 80%
“…In SNNs using analog eNeurons with high f spike , STDP learning curve can be illustrated in Fig. 2 [5], [6], [14]. There, a positive ∆T s less than 1 µs leads to a substantial increase in ∆w syn , while a negative ∆T s higher than -1 µs leads to a strong decrease in ∆w syn .…”
Section: B Stdp Learningmentioning
confidence: 99%
See 1 more Smart Citation