CMOS current steering logic for low-voltage mixed-signal integrated circuits

Ng, Hiok-Tiaq; Allstot, D.J.

doi:10.1109/92.609873

Cited by 64 publications

(4 citation statements)

References 12 publications

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“…In addition, the switching noise of some critical digital blocks was minimized. For instance, a current steering logic [14] is used for token propagation. Moreover, the readout of the memory cells adopts a source follower as the output stage, so that high current injection into the substrate of in-pixel electronics is avoided during the readout.…”

Section: Pixelmentioning

confidence: 99%

Development of a Depleted Monolithic CMOS Sensor in a 150 nm CMOS Technology for the ATLAS Inner Tracker Upgrade

Wang¹,

Rymaszewski²,

Barbero³

et al. 2017

J. Inst.

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The recent R & D focus on CMOS sensors with charge collection in a depleted zone has opened new perspectives for CMOS sensors as fast and radiation hard pixel devices. These sensors, labelled as depleted CMOS sensors (DMAPS), have already shown promising performance as feasible candidates for the ATLAS Inner Tracker (ITk) upgrade, possibly replacing the current passive sensors. A further step to exploit the potential of DMAPS is to investigate the suitability of equipping the outer layers of the ATLAS ITk upgrade with fully monolithic CMOS sensors. This paper presents the development of a depleted monolithic CMOS pixel sensor designed in the LFoundry 150 nm CMOS technology, with the focus on design details and simulation results.

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Section: Pixelmentioning

confidence: 99%

Development of a Depleted Monolithic CMOS Sensor in a 150 nm CMOS Technology for the ATLAS Inner Tracker Upgrade

Wang¹,

Rymaszewski²,

Barbero³

et al. 2017

J. Inst.

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“…V dd has been reduced significantly to maintain the electric field in the channel region. Low-voltage constraint restricts the use of several stacked gates in a CMOS and makes conventional circuits unsuitable [4]. Further, short channel effects degrade small-signal parameters and limit the use of CMOS in sub nanometer era [5].…”

Section: Introductionmentioning

confidence: 99%

An Improved Latch for SerDes Interface: Design and Analysis under PVT and AC Noise

Kumar¹,

Mondal²

2023

RADIOENGINEERING

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Digital subsystem prefers CMOS process, but it is difficult to manage speed and average power (P avg ) trade-off in each era with power supply voltage (V dd ) scaling. Current mode logic (CML) has emerged as an alternative to design the fundamental block of a SerDes, namely, the latch. However, available CML circuits consume significant P avg and suffer from rapid input slewing. Typically, fast switching inputs enable current flow to effective supply voltage V P and overcharges output. In fact, V P is different than externally applied V dd and oscillates with time as and when an abrupt current is drawn. This affects delay t d and introduces jitter. The topic presents a new latch for SerDes interface using a new current steering circuit and coupled to a power delivery network (PDN). The significant point is to attain an almost constant t d in comparison to conventional designs while the V dd changes. The post-layout results at 0.09-μm CMOS and 1.1 V V dd indicate that the P avg and t d are 339.5 µW and 61.9 ps, respectively, at 27°C. Surprisingly, the t d variation is noted to be minimum and the power supply noise induced jitter is around 1.5 ns when V P close to the circuit varies due to sudden current.

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“…Also, CMOS circuit has substantial power consumption which increases with the operating frequency so a different logic style is required [2]. Among the possible topologies [3][4][5][6][7], one of the most successful logic styles is the MOS Current Mode Logic (MCML). The logic style is characterized by low switching noise generation, static power consumption that is independent of frequency and is thus suitable for implementing high-resolution mixed signal integrated circuits operating at high frequencies [8].…”

Section: Introductionmentioning

confidence: 99%

A new current mode logic style with feedback for digital applications

Gupta

Radhakrishnan

Chaudhary

et al. 2011

2011 International Conference on Multimedia, Signal Processing and Communication Technologies

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In this paper, a new logic style named as MOS current mode logic with feedback is proposed as an alternative to conventional MOS current mode logic for implementing digital circuits operating at high frequencies. The proposed circuit style employs a positive feedback that enhances the switching speed of the circuit. The use of feedback reduces the number of transistors needed to implement the circuit in comparison to conventional MOS current mode logic. Different circuits based on MOS current mode logic with feedback are proposed and simulated in PSPICE using 0.18µm CMOS technology parameters. Their performance comparison with CMOS and conventional MCML circuits indicates that the proposed circuits have lesser number of transistors with minimum propagation delay values.

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CMOS current steering logic for low-voltage mixed-signal integrated circuits

Cited by 64 publications

References 12 publications

Development of a Depleted Monolithic CMOS Sensor in a 150 nm CMOS Technology for the ATLAS Inner Tracker Upgrade

Development of a Depleted Monolithic CMOS Sensor in a 150 nm CMOS Technology for the ATLAS Inner Tracker Upgrade

An Improved Latch for SerDes Interface: Design and Analysis under PVT and AC Noise

A new current mode logic style with feedback for digital applications

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