CMOS Detector Technology

Abstract

An entry level overview of state-of-the-art CMOS detector technology is presented. Operating principles and system architecture are explained in comparison to the well-established CCD technology, followed by a discussion of important benefits of modern CMOS-based detector arrays. A number of unique CMOS features including different shutter modes and scanning concepts are described. In addition, sub-field stitching is presented as a technique for producing very large imagers. After a brief introduction to the concept of monolithic CMOS sensors, hybrid detectors technology is introduced. A comparison of noise reduction methods for CMOS hybrids is presented. The final sections review CMOS fabrication processes for monolithic and vertically integrated image sensors.

A line scanning confocal fluorescent microscope using a CMOS rolling shutter as an adjustable aperture

“…An electronic transistor‐transistor logic (TTL) pulse is used to synchronize the laser line scanning and the motion of the RS on the camera for confocal imaging so that both start scanning at the same time. For confocal image capture, the CMOS camera is operated in RS mode (Janesick, 2003; Krymski & Cho, 2004; Hoffman et al , 2006; Holst & Lomheim, 2007) and its movement synchronized with the scanning of the line of emitted fluorescence on the CMOS detector. A CMOS camera can be operated either in global shutter mode, analogous to a CCD chip, in which entire frame of the picture is captured simultaneously, or in RS mode.…”

Characterisation of regional variations in a stitched CMOS active pixel sensor

“…The sensor array was constructed by stepping a sub-block mask of 10.8 mm × 10.8 mm optically across the wafer [9]. The sub-block mask formed a 270 × 270 pixel array (labelled D in figure 1).…”

Design and fabrication of silicon-tessellated structures for monocentric imagers

“…Although current CMOS backend processes can include 10 or more metal interconnect layers, a common APS technique typically contains three or four metal layers for signal processing and readout 20 . We investigate stress in the metal/dielectric stack by adding multiple Al/SiO 2 layers atop a 10-μm Si layer, with each Al/SiO 2 layer consisting of 0.5 μm of Al and 1.5 μm of SiO 2 .…”