CMOS implementation of a 1.6 GHz low voltage low phase noise quadrature output frequency synthesizer with automatic amplitude control

Abstract

This article presents the design of a 1.2 V CMOS low phase noise quadrature output frequency synthesizer (FS) to be used for a GPS tuner application. Special reference is made to the design of a wide tuning range quadrature output voltage-controlled oscillator which is equipped with an automatic amplitude controller. It exhibits a phase noise response of less than -115 dBc/Hz at an offset of 1 MHz from the carrier and has a tuning range of over 36%. The effect of the automatic amplitude control is shown to improve phase noise at high oscillation frequencies and its noise has a negligible effect on the phase noise response even at low offset frequencies from the carrier. Preliminary analysis is presented showing the negligible effect of a DC-DC converter on the spurious level of the FS, included to permit the use of low sensitivity varactors. Design guidelines for reducing both the loop noise and the AM-to-PM conversion factors of the oscillator are also given. The design was made using the STMicroelectronics 0.13 lm HCMOS9-RF technology design kit.

A temperature stabilized CMOS VCO

“…A differential cross-coupled LC oscillator topology such as Fig. 3 is selected since it is less sensitive to PVT, as well as to common-mode noise interferences [12,13]. An equal amount of bias is provided for both gates of the transistors.…”

Exact analysis of spurious signals in Direct Digital Frequency Synthesizers due to amplitude quantization

“…Efforts for determining the magnitude and spectral location of (only) phase-truncation spurs were reported in Refs. [1,3,8,9] and other publications. These publications describe similar approaches and base their analyses on the phase-error sequence due to phase truncation and, using properties of this error sequence along with the assistance of small-angle approximations, derive a complex procedure for the characterization of phase truncation spurs.…”

“…In addition to the above requirements, hardware designers are targeting more and more cost-saving and power-saving solutions [1,2] . But the most important specification of frequency synthesis is spectral purity [3] . Direct Digital Frequency Synthesizers (DDFSs) are now widely used in modern telecommunications and measurement devices.…”

Experimental results obtained from a 1.6 GHz CMOS quadrature output phase locked loop with on-chip DC-DC converter

“…In [3] apart from employing a switched capacitor bank for the coarse tuning of the oscillator, an on-chip DC-DC converter is used to permit the use of low sensitivity varactors while still achieving the required tuning range. This is beneficial since minimising the tuning gain directly reduces varactor amplitude modulation (AM) to phase modulation (PM) noise conversion and thus a better phase noise response is achieved.…”

“…This is beneficial since minimising the tuning gain directly reduces varactor amplitude modulation (AM) to phase modulation (PM) noise conversion and thus a better phase noise response is achieved. Whilst in [3], the results were limited to those obtained via simulation, the work presented in this paper highlights and discusses the measured results and characterisation of the prototype chip. An on-chip DC-DC converter is not commonly employed in a RFIC due to the possibility of interference with the RF function.…”