CMOS implementation of a new high speed 5-2 compressor for parallel accumulations

Abstract

This paper presents a new high speed 5-2 compressor. It is designed based on a new truth table which leads to a simple structure. Also, the driving problems are reduced. Due to the similar paths from inputs to the outputs, there will be no need for extra buffers in low latency paths to equalize the delays and the power dissipation is decreased. Furthermore, by use of full swing logics, the speed of cascaded operations is enhanced. The latency of proposed design is 440 ps.

Low‐power high‐performance CMOS 5‐2 compressor with 58 transistors

“…Furthermore, it has the lowest power dissipation and PDP, achieving 35.6–64.9% and 48.1–78.8% improvement, respectively. Regarding delay, it is 1.8% slower than [7] and 4.8–46.3% faster than [3–6, 8]. The post‐layout results for our circuit add an overhead of 32.8% in power and 38.5% in delay, compared to pre‐layout simulation.…”

“…The post‐layout results for our circuit add an overhead of 32.8% in power and 38.5% in delay, compared to pre‐layout simulation. Nonetheless, power and PDP are still lower than schematic level implementations of [3–8] and delay is lower than [3, 5, 8].…”

“…Regarding transistor width, transmission gates use equally sized transistors ( W n = W p = 60 nm), whereas in every other case, k stacked nMOS (pMOS) have W n = k × 60 nm ( W p = k × 120 nm). In case of [3, 6], we added some inverters (along with proper modifications) to avoid outputs driven by pass transistors. Therefore, their transistor count is slightly higher than originally reported.…”

“…A 5‐2 compressor was initially used in [2] for the design of a high performance 16 × 16‐bit multiplier, however specific transistor‐level implementation was not provided. Several follow‐up publications proposed new designs for the 5‐2 compressor with different structures and performance trade‐offs [3–8].…”

CMOS High-Performance 5-2 and 6-2 Compressors for High-Speed Parallel Multipliers

“…At least a latency of 5 XOR logic gates (in gate-level) is expected for this realization where with the help of some optimizations reported in [8], the delay has been reduced to 4 XOR gates. Although there are many structures reported in the literature [8,9,10,11,12,13,14], none of them have been able to reach latencies less than 4 XOR gates. This partially comes down to the lack of deep consideration and investigation of the original truth table for the 5-2 compressor block.…”