CMOS Logic and Capacitorless DRAM by Stacked Oxide Semiconductor and Poly-Si Transistors for Monolithic 3-D Integration

Wang, Ziheng; Zheng, Liankai; Lin, Zhiyu; Zhao, Jinxiu; Tang, Wei; Feng, Linrun; Liu, Zhe; Li, Xuefei; Guo, Xiaojun; Si, Mengwei

doi:10.1109/ted.2024.3418768

IEEE Trans. Electron Devices

2024

DOI: 10.1109/ted.2024.3418768

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CMOS Logic and Capacitorless DRAM by Stacked Oxide Semiconductor and Poly-Si Transistors for Monolithic 3-D Integration

Ziheng Wang,

Liankai Zheng,

Zhiyu Lin

et al.

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Voltage Stacking: A First-Order Modelization of an m × n Asynchronous Array for Chip and Architectural Design Exploration

Chauviere,

Stevens

2024

JLPEA

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Voltage stacking is a technique in which multiple integrated circuits are stacked in series between the supply voltage instead of in parallel, thus improving the energy efficiency of the power distribution network. Unfortunately, voltage stacking presents stability challenges for integrated circuits within the stack. A first-order model to quantify variability, stability, and power metrics for an array of voltage-stacked asynchronous integrated circuits is presented. Voltage variability and power consumption are accounted for and discussed. Limitations of the model are identified outside of the nominal behavior. The number of columns in the architecture, chip leakage, and supply voltage are shown to be the key contributors to the stability, performance, and energy efficiency of a system of voltage-stacked asynchronous processors. A higher leakage to active power ratio, though usually avoided by chip designers, is shown to improve stability and be key in designing stacks without external balancing. Outputs of the model enable system and chip designers to evaluate first-order trade-offs in energy efficiency, performance, and system cost. These fundamental data allow designers to make informed design and optimization trade-offs between asynchronous voltage-stacked architectures and the integrated circuits used therein. Analysis of this model shows that various voltage-stacked configurations, such as one with a 48 V supply using 100 rows and 11 columns, can be designed with less than 10% voltage variation per chip, mitigating the need for external voltage balancing.

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Voltage Stacking: A First-Order Modelization of an m × n Asynchronous Array for Chip and Architectural Design Exploration

Chauviere,

Stevens

2024

JLPEA

View full text Add to dashboard Cite

show abstract

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CMOS Logic and Capacitorless DRAM by Stacked Oxide Semiconductor and Poly-Si Transistors for Monolithic 3-D Integration

Cited by 1 publication

References 32 publications

Voltage Stacking: A First-Order Modelization of an m × n Asynchronous Array for Chip and Architectural Design Exploration

Voltage Stacking: A First-Order Modelization of an m × n Asynchronous Array for Chip and Architectural Design Exploration

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