“…In the earlier stage, the CMOS MEMS process had a larger CD or minimum line width in the academic labs of Europe and USA [73][74][75][76][77][78][79][80]. As the CD kept on decreasing to 0.8 µm [35] or even smaller than 0.6 µm [90,113] Fabrication technologies during CMOS and CMOS MEMS processes include thermal conversion [94,[141][142][143][144][145], chemical vapor deposition (CVD) [4,80,134], epitaxy [32,[146][147][148][149][150], physical vapor deposition (PVD) [151][152][153][154][155], atomic layer deposition (ALD) [156,157], spin-on films/dielectrics [158][159][160], bulk micromachining [161], surface micromachining [51,113,135,162], photolithography module [163], dry etching, and wet etching. Most of the materials used for structural, sacrificial and passivation layers include silicon and its oxide, nitride, silicon-germanium, carbide derivatives, and other notable semiconductor and dielectric materials [133,…”