2010
DOI: 10.1007/s00034-010-9197-1
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CMOS Readout Circuit with New Background Suppression Technique for Room-Temperature Infrared FPA Applications

Abstract: A high-performance CMOS readout integrated circuit (ROIC) with a new temperature and power supply independent background current and dark current suppression technique for room-temperature infrared focal plane array applications is proposed. The structure is composed of an improved switched current integration stage, a new current-mode background suppression circuit, and a high linearity, high voltage swing output stage. An experimental readout chip has been designed and fabricated using the Chartered 0.35 µm … Show more

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Cited by 9 publications
(2 citation statements)
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“…From equation (15), the value of R Z will control the RHP zero and equal 1/g m6 to eliminate it. Now, the resistance R Z will be replaced by a transistor M9 so the aspect ratio (S 9 ) of transistor M9 can be determined by [21]:…”
Section: Design Of the Op-ampmentioning
confidence: 99%
See 1 more Smart Citation
“…From equation (15), the value of R Z will control the RHP zero and equal 1/g m6 to eliminate it. Now, the resistance R Z will be replaced by a transistor M9 so the aspect ratio (S 9 ) of transistor M9 can be determined by [21]:…”
Section: Design Of the Op-ampmentioning
confidence: 99%
“…Basically, the DR is limited by the maximum integration voltage (V max ), the integration capacitor (C int ) and the readout noise of the circuit as shown in equation (1) [15] where, q is the electron charge. The DR can be widened either by changing the C int values [4][5][6][7][8][9][10][11][12][13][14][15][16], or by changing the integration time [9,12]. (1) This paper concerns with the application of a new widening DR technique to the CTIA ROIC based on the CDS circuit with emphasis on its power consumption and noise performance compared to other works.…”
Section: Introductionmentioning
confidence: 99%