CMOS Technology Scaling Considerations for Multi-Gbps Optical Receivers With Integrated Photodetectors

Carusone, Anthony Chan; Yasotharan, Hemesh; Kao, Tsung-Hsien

doi:10.1109/jssc.2011.2157254

Cited by 25 publications

(14 citation statements)

References 22 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Together with an optimized design of the emitter (implemented as stripes) high RBPs were achieved. The maximum achieved RBP of 171.1 A/W*MHz (9.4 A/W, 18.2 MHz) is several hundred times larger than that for the PTs presented in [5] and more than a factor of 3 better than the PTs presented in [6]. The presented PT is well suited for integration into an optoelectronic integrated circuit (OEIC).…”

Section: Discussionmentioning

confidence: 84%

Integrated 180 nm CMOS phototransistors with an optimized responsivity-bandwidth-product

Kostov

Gaberl

Hofbauer

et al. 2012

IEEE Photonics Conference 2012

View full text Add to dashboard Cite

A phototransistor with an optimized responsivitybandwidth-product is presented in this paper. The device has a size of 40×40 µm 2 and is implemented in a standard 180 nm CMOS process. By means of a thick low doped p-epitaxial layer starting material (collector), a base formed as striped n-wells and an optimized design of the emitter high responsivity-bandwidthproduct values up to 171.1 A/W*MHz are achieved.

show abstract

Section: Discussionmentioning

confidence: 84%

Integrated 180 nm CMOS phototransistors with an optimized responsivity-bandwidth-product

Kostov

Gaberl

Hofbauer

et al. 2012

IEEE Photonics Conference 2012

View full text Add to dashboard Cite

show abstract

“…The bandwidth could be extended to reasonable values for detectors with rather small areas but at the expense of reduced detector responsivity, quotient of photogenerated current and received light power. The responsivity of the detector and the input-referred noise current density of the first amplifier stage (in most cases a TIA) are crucial for the sensitivity of an optical receiver [18] leading to a rather bad sensitivity of the nanometer-CMOS OEICs reported in [11] and [13]. The responsivity depends mainly on the wavelength of the incident radiation, on the PD's properties like the bandgap of the PD's material, the reflection, and the transmission in the isolation and passivation stack on the PD.…”

Section: Pin Photodiodementioning

confidence: 99%

PIN Photodiode Optoelectronic Integrated Receiver Used for 3-Gb/s Free-Space Optical Communication

Brandl

Schidl

Zimmermann

2014

IEEE J. Select. Topics Quantum Electron.

View full text Add to dashboard Cite

In this paper, an optoelectronic integrated receiver chip including five PIN photodiodes will be presented. A large 200-μm diameter photodiode connected to a high-speed transimpedance amplifier works as a 3-Gb/s receiver for optical wireless communication. Four surrounding photodiodes allow for the adjustment of the incoming laser ray. The complete chip was realized in a silicon 0.35-μm BiCMOS technology to benefit from the available intrinsic zone in this technology. Due to this intrinsic zone and an antireflection coating, the responsivity reaches a value of more than 0.5 A/W for wavelengths from 630 to 760 nm. Furthermore, the capacitance of the center photodiode is less than 0.6 pF for reverse bias voltages larger than 3 V. For proof of concept, a steerable and adjustable light source was built based on a micro-electro-mechanical system mirror, on a focusing unit, and on a direct modulated vertical cavity surface emitting laser with a wavelength of 680 nm. The complete system is capable of establishing a 3-Gb/s data transfer over a distance of 19 m at a BER of <10 −9 , and over a distance of 18 m at a BER of <10 −12 .

show abstract

“…4. One goal of our research is to characterize both the electrical extrinsic and optical intrinsic parameters of the proposed PD [4], [12], so that we can build a model for the PD. Then, with the PD model, the co-simulation of PD and the following receiver circuits can be performed seamlessly.…”

Section: Responsivity =mentioning

confidence: 99%

A 0.5-V P-Well/Deep N-Well Photodetector in 65-nm CMOS for Monolithic 850-nm Optical Receivers

Pan

Hou

Liu

et al. 2014

IEEE Photon. Technol. Lett.

View full text Add to dashboard Cite

This letter presents the design, measurement results, and modeling formula of a P-well/deep N-well photodetector (PD) realized in a standard 65-nm complementary metal-oxidesemiconductor without process modification. With 0.5-V reverse bias (V PD ), the measured dc responsivity to an 850-nm light source is 51 mA/W and the −3-dB bandwidth is 500 MHz. Besides, a seamless cosimulation of the PD and the following receiver circuits are presented. Optical measurement results show that under 0.5-V V P D , the optical receiver achieves a new record data rate of 9 Gb/s for 2 15 -1 pseudorandom binary sequence with 10 −12 bit error rate and −4.2-dBm optical input sensitivity.Index Terms-CMOS photodetector, responsivity, frequency response, CMOS integrated optical receiver.

show abstract

CMOS Technology Scaling Considerations for Multi-Gbps Optical Receivers With Integrated Photodetectors

Cited by 25 publications

References 22 publications

Integrated 180 nm CMOS phototransistors with an optimized responsivity-bandwidth-product

Integrated 180 nm CMOS phototransistors with an optimized responsivity-bandwidth-product

PIN Photodiode Optoelectronic Integrated Receiver Used for 3-Gb/s Free-Space Optical Communication

A 0.5-V P-Well/Deep N-Well Photodetector in 65-nm CMOS for Monolithic 850-nm Optical Receivers

Contact Info

Product

Resources

About