2004
DOI: 10.1016/j.tsf.2003.07.028
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CMP of ultra low-k material porous-polysilazane (PPSZ) for interconnect applications

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Cited by 13 publications
(10 citation statements)
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“…Dong-Pyo et al [7] investigated the etching behaviour of Bi 4−x La x Ti 3 O 12 (BLT) films in inductively coupled Ar/Cl 2 plasma in terms of etch parameters. They found that the etching rate as a function of mixing ratio showed a maximum of 50.3 nm min −1 for a mixture of 80% Ar and 20% Cl 2 and that the increase of source power or substrate bias caused an increase in BLT etch rate under any fixed gas composition.…”
Section: Introductionmentioning
confidence: 99%
“…Dong-Pyo et al [7] investigated the etching behaviour of Bi 4−x La x Ti 3 O 12 (BLT) films in inductively coupled Ar/Cl 2 plasma in terms of etch parameters. They found that the etching rate as a function of mixing ratio showed a maximum of 50.3 nm min −1 for a mixture of 80% Ar and 20% Cl 2 and that the increase of source power or substrate bias caused an increase in BLT etch rate under any fixed gas composition.…”
Section: Introductionmentioning
confidence: 99%
“…The fabrication process for PPSZ films can be divided into 3 steps. 5) First, PPSZ precursors are spun on Si substrates at 2000 rpm for 30 s by a spin coater. This followed by softbaking steps at 150 and 280 C for 3 min to remove solvent.…”
Section: Fabrication and Properties Of Ppsz Filmsmentioning
confidence: 99%
“…During the hydration step, there are two mechanisms, hydrolysis and condensatio, by which the polymer structure is transformed into porous MSQ. 4,5) Various hydration times can be used to change the porosities of PPSZ films. Subsequently, the wafers are cured in a quartz furnace at 400 C for 30 min with N 2 purging.…”
Section: Fabrication and Properties Of Ppsz Filmsmentioning
confidence: 99%
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“…On the other hand, as device nodes progress and the number of applications of CMP in semiconductor device manufacturing increases, defect control is becoming another key factor in CMP. [13][14][15] From this viewpoint, the development of a low-k Cu interconnect process is a challenge because low-k films 16,17) are fragile and easily peel off especially at the wafer edge portion. 18) Therefore, wafer edge pressure control by adjusting the retainer ring pressure is also considered important for preventing low-k film delamination.…”
Section: Introductionmentioning
confidence: 99%