CNFET-based high throughput register file architecture

Exploring emerging CNFET for efficient last level cache design

“…A micro-architectural timing model was proposed in [23] to evaluate the delay distribution of different CNFET layouts. On top of the models, Li Jiang et al in [24] [25] explored the CNFET-based design of modern SIMD register files and proposed a novel register assignment method to take advantage of the delay variation caused by the asymmetrically correlated variation. Patil et al [11] proposed a VLSI-compatible metallic CNT removal (VMR) approach to create basic CNFET circuits such as half-adders and D-latches immune to CNT imperfections.…”