CNTFET-based design of ternary logic gates with interchangeable standard positive and negative ternary output

Abstract

This paper presents a novel CNTFET based design of ternary logics gates where all three ternary logics including standard, positive and negative ternary logic (ST, PT and NT) outputs for each gate are obtained from one structure and are interchangeable through some control inputs. Ternary logic overpowers the conventional binary logic in simplicity and energy efficiency as it reduces number of interconnects and chip area. In this paper design of ternary inverter, buffer, NAND, AND, NOR, OR, XOR and XNOR gates are presented where a unique feature of conversion between ST, PT, NT logic through a single output is being introduced. Besides a single logic gate is designed for a particular logic function and its complement combining both ternary and binary logic gate design technique. The proposed designs utilize the unique property of CNTFET, such as assigning the required threshold voltage value of the FET by changing the diameter of the carbon nanotube (CNT) through its chiral vector values which is very useful in designing multiple-valued logic (here ternary logic). The proposed circuits are simulated using Synopsys HSPICE with 32 nm CNTFET model provided by Stanford University and in each case average power values and propagation delays are duly noted. The effects of variation in some process parameters like channel length, dielectric oxide thickness and number of carbon nanotubes also have been discussed.

Low power CNTFET-based ternary multiplier for digital signal processing applications

“…The high storage density of each line leads to effective utilization of transmission channels. Using ternary logic, high-speed serial-parallel arithmetic transfer can be achieved [25].…”

Variability aware ultra-low power design of NOR/NAND gate using non-conventional techniques

“…It is explained in the literature [8][9][10] that the success probability of desired outputs in OR-NOR, AND-NAND, and latch operations remains reliable despite the correlation between internal and external noise. A pioneering design of ternary logic gates using CNTFETs is introduced in [11]. The proposed design encompasses all three ternary logics-standard, positive, and negative ternary logic (ST, PT, and NT)-with outputs for each gate derived from a single structure.…”