CNTFET SRAM cell design with tolerance to metallic CNTs

Zhang, Zhe; Delgado-Frias, J.G.; Nyathi, J.

doi:10.1109/mwscas.2010.5548846

Cited by 5 publications

(6 citation statements)

References 12 publications

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“…Moreover, because the 11T one has subthreshold operation at nodes Q and QN, the voltage level of Logic‐1 in RBL is below

{V}_{\text{DD}}

and

{V}_{\text{th}}

, which is not suitable for sensing by next devices or peripherals. Note that other CNTFET works employed similar decoupled R/W BLs circuits without

{X}_{9}

{X}_{10}

, did not face these problems because of using ‘

{V}_{\text{DD}}

{V}_{\text{th}}

’ in their designs [34–47]. This 11T bitcell (Figure 7) just solves ‘read‐mode discharges (distortions)’, but it increases the ‘overshoots/undershoots (spikes)’ and cannot solve ‘the drop of Logic‐1 voltage‐level in read mode’.…”

Section: Design and Analysismentioning

confidence: 99%

“…Also, it has an acceptable leakage current and static/dynamic powers (Table 3). Note that other works were not designed for operating at threshold supply‐voltage (

{V}_{\text{DD}}

{V}_{\text{th}}

), as well as, they just reduced their delays at the cost of higher power‐consumptions [10–75] which are not suitable for implementing in chipset of portable devices. As a result, this 11T bitcell (Figure 9) can be considered as a final optimum design that this paper tries to reach it from the beginning.…”

Section: Design and Analysismentioning

confidence: 99%

“…In recent decades, many efforts have been made by researchers to offer optimum designs for bitcell. They declared that thanks to the CNTs, CNTFETs have been considered as a promising alternative for Complementary Metal Oxide Semiconductors (CMOSs) in low power SRAMs [10–75], however, CNFET fabrication process still has some imperfections, including the presence of metallic carbon nanotubes ( m ‐CNTs), imperfect m ‐CNT removal processes, chirality drift, CNT doping variations, and density fluctuations, etc. [76–79].…”

Section: Introductionmentioning

confidence: 99%

“…Some of them exhibited comparative works to show the advantages of CNTFETs over CMOSs and FinFETs in bitcells due to extensive electrical properties of CNTs and excellent characteristics of CNTFETs [42–61]. They also reported that bitcells suffered from leakage power [10, 12, 36, 66, 67], Delay [36, 66–69], worse Read SNM [34, 49, 52, 66], negative impacts of nearthreshold supply voltage on delays and SNM [41, 68], subthreshold leakage currents [57], etc., and suggested different techniques, such as ‘decoupled R/W BLs’ [34–47, 66, 68] and ‘power‐gating’ [41, 42, 63–65], to solve those problems.…”

Section: Introductionmentioning

confidence: 99%

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Challenges and solutions of working under threshold supply‐voltage, for CNTFET‐based SRAM‐bitcell

Shahrabadi

2022

IET Circuits, Devices & Syst

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Recently, several studies were done on SRAM bitcells at different supply‐voltages; upper, near or lower to threshold voltage. To the best of the author's knowledge, none of them discussed at threshold supply‐voltage with proper subthreshold operations and Nano/Pico power‐dissipations, hence this paper decides to investigate challenges and solutions of designing at VboldDboldD ${\mathbf{V}}_{\mathbf{D}\mathbf{D}}$ = Vboldtboldh ${\mathbf{V}}_{\mathbf{t}\mathbf{h}}$, because this voltage will lead to having lower power consumptions. This research applies power‐gating technique to adjust VboldDboldD ${\mathbf{V}}_{\mathbf{D}\mathbf{D}}$ on Vboldtboldh ${\mathbf{V}}_{\mathbf{t}\mathbf{h}}$, and also utilises output‐inverter to set Logic 1 at VboldDboldD ${\mathbf{V}}_{\mathbf{D}\mathbf{D}}$. Although ‘power‐gating’ and ‘output‐inverter’ were used in other works, this study renders specific points about them. In fact, the ability of power‐gating technique in adjusting VboldDboldD ${\mathbf{V}}_{\mathbf{D}\mathbf{D}}$ on Vboldtboldh ${\mathbf{V}}_{\mathbf{t}\mathbf{h}}$ without any instabilities in bitcell operation was not reported before, as well as, the idea of employing output‐inverter in read path for setting Logic‐1 at VboldDboldD ${\mathbf{V}}_{\mathbf{D}\mathbf{D}}$. It also proposed SNM% as a useful figure‐of‐merit. The goal of this study is not to present new circuits for bitcell, but is to investigate challenges and solutions of working under ‘VboldDboldD=Vboldtboldh ${\mathbf{V}}_{\mathbf{D}\mathbf{D}}={\mathbf{V}}_{\mathbf{t}\mathbf{h}}$’ which these solutions can lead to having an optimum bitcell.

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“…Moreover, because the 11T one has subthreshold operation at nodes Q and QN, the voltage level of Logic‐1 in RBL is below

{V}_{\text{DD}}

and

{V}_{\text{th}}

, which is not suitable for sensing by next devices or peripherals. Note that other CNTFET works employed similar decoupled R/W BLs circuits without

{X}_{9}

{X}_{10}

, did not face these problems because of using ‘

{V}_{\text{DD}}

{V}_{\text{th}}

Section: Design and Analysismentioning

confidence: 99%

“…Also, it has an acceptable leakage current and static/dynamic powers (Table 3). Note that other works were not designed for operating at threshold supply‐voltage (

{V}_{\text{DD}}

{V}_{\text{th}}

Section: Design and Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Challenges and solutions of working under threshold supply‐voltage, for CNTFET‐based SRAM‐bitcell

Shahrabadi

2022

IET Circuits, Devices & Syst

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“…In [10], the authors have compared graphene nanoribbon field effect transistor (GNRFET) based SRAM with silicon FET based SRAM and showed the power consumption of GNRFET with respect to silicon based SRAM. In [11], the authors have considered the effect of metallic CNT on the read and write delay. However they have completely ignored the effects on power and the noise margin.…”

Section: Introductionmentioning

confidence: 99%

Comparative Analysis of 6T, 7T, 8T, 9T, and 10T Realistic CNTFET Based SRAM

Joshi

Alabawi

2017

Journal of Nanotechnology

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CMOS technology below 10 nm faces fundamental limits which restricts its applicability for future electronic application mainly in terms of size, power consumption, and speed. In digital electronics, memory components play a very significant role. SRAM, due to its unique ability to retain data, is one of the most popular memory elements used in most of the digital devices. With aggressive technology scaling, the design of SRAM is seriously challenged in terms of delay, noise margin, and stability. This paper compares the performance of various CNTFET based SRAM cell topologies like 6T, 7T, 8T, 9T, and 10T cell with respect to static noise margin (SNM), write margin (WM), read delay, and power consumption. To consider the nonidealities of CNTFET, variations in tube diameter and effect of metallic tubes are considered for various structures with respect to various performance metrics like SNM, WM, read delay, and power consumption.

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