Co-design of channel buffers and crossbar organizations in NoCs architectures

Kodi,; Morris, Craig F.; DiTomaso,; Sarathy,; Louri,

doi:10.1109/iccad.2011.6105329

Cited by 4 publications

(2 citation statements)

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“…In order to have the same amount of buffering as a conventional 4 VC/input router, we place a set of N =4 links between routers each consisting of two channel buffer lines. Each link consists of two channel buffer lines to alleviate HoL blocking [7]. Additionally, since QORE has more links between routers than the two links in conventional routers, we have reduced the bandwidth of our links for a fair comparison, as explained in the evaluation section.…”

Section: A Qfc Without Faultsmentioning

confidence: 99%

“…Research has shown that router buffers are responsible for 46% of router power [5] and 30% of router area [6]. This has motivated architects to implement buffer optimization techniques such as elastic buffering [7], [8], [9] and bufferless routing [10], [11]. By completely eliminating buffers and implementing bufferless routing, recent work has reduced the average network energy by 40% [10].…”

Section: Introductionmentioning

confidence: 99%

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QORE: A fault tolerant network-on-chip architecture with power-efficient quad-function channel (QFC) buffers

DiTomaso

Kodi

Louri

2014

2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)

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Network-on-Chips (NoCs) are quickly becoming the standard communication paradigm for the growing number of cores on the chip. While NoCs can deliver sufficient bandwidth and enhance scalability, NoCs suffer from high power consumption due to the router microarchitecture and communication channels that facilitate inter-core communication. As technology keeps scaling down in the nanometer regime, unpredictable device behavior due to aging, infant mortality, design defects, soft errors, aggressive design, and process-voltage-temperature variations, will increase and will result in a significant increase in faults (both permanent and transient) and hardware failures. In this paper, we propose QORE -a fault tolerant NoC architecture with Quad-Function Channel (QFC) buffers. The use of QFC buffers and their associated control (link and fault controllers) enhance fault-tolerance by allowing the NoC to dynamically adapt to faults at the link level and reverse propagation direction to avoid faulty links. Additionally, QFC buffers reduce router power and improve performance by eliminating in-router buffering. Our simulation results using real benchmarks and synthetic traffic mixes show that QORE improves speedup by 1.3× and throughput by 2.3× when compared to state-of-the art fault tolerant NoCs designs such as Ariadne and Vicis. Moreover, using Synopsys Design Compiler, we also show that network power in QORE is reduced by 21% with minimal control overhead.

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Section: A Qfc Without Faultsmentioning

confidence: 99%