Co-evolutionary Approach to Reduce Soft Error Rate of Implemented Circuits on SRAM_based FPGA

Abstract

Soft errors such as Single Event Upset (SEU) have great effect on performance degradation of circuits implemented on SRAM_based FPGA. The soft error in configuration bits which control the logic and routing parts of the circuit, leads to permanent faults. In this paper, we have developed a coevolutionary method to reduce the effect of soft error on the implemented circuit on FPGA. This method is based on cooperation of genetic algorithm and ant colony optimization. The efficiency of co-evolutionary method has been proved by comparison of its results with the proposed genetic algorithm and ant colony optimization. The experimental results for some MCNC benchmark circuits show up to 34% improvement compare to genetic algorithm and up to 60% improvement against ant colony optimization.

Hybrid genetic‐paired‐permutation algorithm for improved VLSI placement

“…For example, in [12,13], evolutionary and co-evolutionary methods were developed to reduce the soft error rate, which applies to chips in aerospace applications. The proposed methods were based on a GA and particle swarm optimization (PSO) and improved the convergence rate and cost of the former methods.…”