Co-scheduling aperiodic real-time tasks with end-to-end firm and soft deadlines in two-stage systems

Leng, Chang; Qiao, Ying; Hu, Xiaobo Sharon; Wang, Hongan

doi:10.1007/s11241-020-09352-1

Cited by 7 publications

(5 citation statements)

References 38 publications

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“…Consequently, the proposed RISC core not only provides complicated cryptographic operations but also leads to power analysis resistance with complex masked operations without additional custom instructions. In order to reduce the real run-time overhead, the authors propose in [14] a quasi-sharing-based scheduling algorithm, called qHS-2S-RTS, which can achieve equivalent scheduling performance to HS-2S-RTS. A new control algorithm for HS-2S-RTS and qHS-2S-RTS, called HSAC-2S-RTS, is also designed.…”

Section: Related Workmentioning

confidence: 99%

“…The proposed vector processor can be scaled to meet the performance requirements of massively parallel computational tasks, but its timing behavior can remain simple enough to be efficiently analyzable. The same idea from existing studies is the improvement or proposal of new scheduling algorithms [9], [14], [15], [17], [18], [20] and their implementation in hardware or in hybrid form for processor acceleration. Another similar idea introduced in articles [10], [11], [12], [16], HW_nMPRA_RTOS, is to integrate operating system functions, schedulers or external accelerators in hardware, which are then integrated into real-time or even mixed-criticality systems.…”

Section: Related Workmentioning

confidence: 99%

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Custom Soft-Core RISC Processor Validation Based on Real-Time Event Handling Scheduler FPGA Implementation

Zagan

Găitan

2023

IEEE Access

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In dynamic real-time systems (RTS), the synchronous communication model is a source of unpredictable behaviors caused by the difficulty of estimating the maximum lockdown time in a process. Inter-task communication is a critical issue in RTS, even in the case of uniprocessor architectures. Using an FPGA-based development platform, through an SoC project, the implementation of HW_nMPRA_RTOS (a unified acronym for multi pipeline register architecture (nMPRA) where n is the degree of datapath resource multiplication, hardware scheduler engine (nHSE) for n threads and RTOS application programming interface (API)), dedicated processor architecture was developed, simulated and validated. This paper propose an innovative soft-core implementation to reduce interrupt latencies, while maintaining strong spatial and temporal isolation. Among the results which contain relevance and novelty, we can mention: rapid tasks context switching (1 clock cycle); The implementation of a distributed and versatile interrupt system which allows the interrupt attachment to any task; The implementation of a static scheduler and support for the dynamic tasks scheduling; Rapid response to events of up to 2 clock cycles. We demonstrate the architecture's predictability, scalability, and performance by running a set of benchmark applications on several configurations of HW_nMPRA_RTOS synthesized on a Xilinx 7 Series FPGA.INDEX TERMS Hardware RTOS, microprocessor, scheduling, field-programmable gate arrays (FPGA), real-time systems

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Custom Soft-Core RISC Processor Validation Based on Real-Time Event Handling Scheduler FPGA Implementation

Zagan

Găitan

2023

IEEE Access

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“…This article addresses specific scheduling methods within two-stage real-time systems (2S-RTS) that schedule and execute aperiodic tasks considering firm and soft deadlines ( Leng et al, 2020 ). The authors propose and validate a new sharing-based heuristic scheduling algorithm called HS-2S-RTS.…”

Section: Related Workmentioning

confidence: 99%

Soft-core processor integration based on different instruction set architectures and field programmable gate array custom datapath implementation

Zagan

Găitan

2023

PeerJ Computer Science

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One of the fundamental requirements of a real-time system (RTS) is the need to guarantee re-al-time determinism for critical tasks. Task execution rates, operating system (OS) overhead, and task context switching times are just a few of the parameters that can cause jitter and missed deadlines in RTS with soft schedulers. Control systems that are susceptible to jitter can be used in the control of HARD RTS as long as the cumulative value of periodicity deviation and worst-case response time is less than the response time required by that application. This artcle presents field-programmable gate array (FPGA) soft-core processors integration based on different instruction set architectures (ISA), custom central processing unit (CPU) datapath, dedicated hardware thread context, and hardware real-time operating system (RTOS) implementations. Based on existing work problems, one parameter that can negatively influence the performance of an RTS is the additional costs due to the operating system. The scheduling and thread context switching operations can significantly degrade the programming limit for RTS, where the task switching frequency is high. In parallel with the improvement of software scheduling algorithms, their implementation in hardware has been proposed and validated to relieve the processor of scheduling overhead and reduce RTOS-specific overhead.

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“…Parallel and distributed computing is extensively used for applications with high computing and storage demands as mentioned in a recent publication (Blej and Azizi, 2019). Many technologies such as cloud computing, the Internet of Things, fog computing, Big data, machine learning used distributed and parallel computers for processing real-time data (Leng et al, 2020). The real-time distributed system implement using real-time tasks scheduling on the distributed system used partitioned and partitioned scheduling (Hluchy et al, 2001).…”

Section: Prior Workmentioning

confidence: 99%

Cluster Based Real Time Scheduling for Distributed System

Talmale¹,

Shrawankar²

2021

ADCAIJ

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Real time tasks scheduling on a distributed system is a complex problem. The existing real time tasks scheduling techniques are primarily based on partitioned and global scheduling. In partitioned based scheduling the tasks are assigned on a dedicated processor. The advantages of partitioned based approach is existing uni-processor scheduling techniques can be used; no migration overheads but task assignment is NP hard problem and optimal utilization of processing nodes is not possible. In global scheduling all tasks are maintained in a single tasks queue and allocated to multiple processing nodes. The advantage of global scheduling is optimal utilization of processing nodes but suffer from high migration and preemption overheads. This paper proposed cluster based real time tasks scheduling on a distributed system which is a hybrid scheduling approach where processing nodes group into cluster and scheduling using global scheduling. The simulation result shows that the proposed scheduling increases the tasks acceptance ratio, resource utilization as compared to partitioned and global scheduling and reduces migration as well as preemption overheads.

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Co-scheduling aperiodic real-time tasks with end-to-end firm and soft deadlines in two-stage systems

Cited by 7 publications

References 38 publications

Custom Soft-Core RISC Processor Validation Based on Real-Time Event Handling Scheduler FPGA Implementation

Custom Soft-Core RISC Processor Validation Based on Real-Time Event Handling Scheduler FPGA Implementation

Soft-core processor integration based on different instruction set architectures and field programmable gate array custom datapath implementation

Cluster Based Real Time Scheduling for Distributed System

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