Coarse-grained Dynamically Reconfigurable Processor for Vision Pre-Processing

Bin, Zhang; Mei, Kuizhi; Zheng, Nanning

doi:10.1007/s11265-013-0828-1

Cited by 5 publications

(6 citation statements)

References 14 publications

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“…For proper switching of BRAM, the above-mentioned clock timings must conform BRAM timing constraints imposed by three parameters: Setup time (T setup ), hold time (T hold ) and clock to out time (T clock−to−out ) [24]. The T setup , T hold , and T clock−to−out of BRAM for Artix-7 is 0.45 ns, 0.31 ns and 0.64 ns respectively [34].…”

Section: ) Duty Cycle Based Bram Accessing Techniquementioning

confidence: 99%

“…This solution is suitable for implementing on-chip buffers for several practical applications. To evaluate its effectiveness in practical designs, let us consider three exemplary applications from literature [23], [24]. Table 2 shows the implementation outcomes in terms of number of BRAM required by our design to buffer pixels data for the chosen applications along with its total power consumption, and also compares the result with conventional methods reported in [18], [25].…”

Section: Demonstration Of Proposed Image Buffering Architecture Fomentioning

confidence: 99%

“…15.8 * 4mW). Let us consider another application for implementing a vision pre-processing task [24]. This pre-processing task is comprised of four 7×7 Gabor filters.…”

Section: Demonstration Of Proposed Image Buffering Architecture Fomentioning

confidence: 99%

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Resource-Efficient Image Buffer Architecture for Neighborhood Processors

et al. 2020

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Neighborhood image processing operations on Field Programmable Gate Array (FPGA) are considered as memory intensive operations. Large memory bandwidth is required to transfer the required pixel data from external memory to the processing unit. On-chip image buffers are employed to reduce this data transfer rate. Conventional image buffers, implemented either by using FPGA logic resources or embedded memories are resource inefficient. They exhaust the limited FPGA resources quickly. Consequently, hardware implementation of neighborhood operations becomes expensive, and integrating them in resource constrained devices becomes unfeasible. This paper presents a resource efficient FPGA based on-chip buffer architecture. The proposed architecture utilizes full capacity of a single Xilinx Block-RAM (BRAM36 primitive) for storing multiple rows of input image. To get multiple pixels/clock in a user defined scan order, an efficient duty-cycle based memory accessing technique is coupled with a customized addressing circuitry. This accessing technique exploits switching capabilities of BRAM to read 4 pixels in a single clock cycle without degrading system frequency. The addressing circuitry provides multiple pixels/clock in any user defined scan order to implement a wide range of neighborhood operations. With the saving of 83% BRAM resources, the buffer architecture operates at 278 MHz on Xilinx Artix-7 FPGA with an efficiency of 1.3 clock/pixel. It is thus capable to fulfill real time image processing requirements for HD image resolution (1080×1920) @103 fps.

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Section: ) Duty Cycle Based Bram Accessing Techniquementioning

confidence: 99%

Section: Demonstration Of Proposed Image Buffering Architecture Fomentioning

confidence: 99%

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Resource-Efficient Image Buffer Architecture for Neighborhood Processors

et al. 2020

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“…On the other hand, hardware platforms such as Application Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA) are high performance and fast. They satisfy the real time image processing requirements and thus received a great deal of attention for implementing filters in these areas [12, 13]. …”

Section: Introductionmentioning

confidence: 99%

A Low Cost Structurally Optimized Design for Diverse Filter Types

et al. 2016

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A wide range of image processing applications deploys two dimensional (2D)-filters for performing diversified tasks such as image enhancement, edge detection, noise suppression, multi scale decomposition and compression etc. All of these tasks require multiple type of 2D-filters simultaneously to acquire the desired results. The resource hungry conventional approach is not a viable option for implementing these computationally intensive 2D-filters especially in a resource constraint environment. Thus it calls for optimized solutions. Mostly the optimization of these filters are based on exploiting structural properties. A common shortcoming of all previously reported optimized approaches is their restricted applicability only for a specific filter type. These narrow scoped solutions completely disregard the versatility attribute of advanced image processing applications and in turn offset their effectiveness while implementing a complete application. This paper presents an efficient framework which exploits the structural properties of 2D-filters for effectually reducing its computational cost along with an added advantage of versatility for supporting diverse filter types. A composite symmetric filter structure is introduced which exploits the identities of quadrant and circular T-symmetries in two distinct filter regions simultaneously. These T-symmetries effectually reduce the number of filter coefficients and consequently its multipliers count. The proposed framework at the same time empowers this composite filter structure with additional capabilities of realizing all of its Ψ-symmetry based subtypes and also its special asymmetric filters case. The two-fold optimized framework thus reduces filter computational cost up to 75% as compared to the conventional approach as well as its versatility attribute not only supports diverse filter types but also offers further cost reduction via resource sharing for sequential implementation of diversified image processing applications especially in a constraint environment.

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“…In addition, a parallel convolver has been implemented on an FPGA device. A reconfigurable architecture for convolution is proposed in this study on basis of our previous work [23]. The proposed processor can simultaneously compute several convolution kernels.…”

Section: Introductionmentioning

confidence: 99%

Hardware Implementation of Reconfigurable 1D Convolution

Rao

Bin

Zhao

2015

J Sign Process Syst

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Convolution has been extensively used in image processing and computer vision, including image enhancement, smoothing, and structure extraction. However, convolution operation typically requires a significant amount of computing resources. A novel one-dimensional (1D) convolution processor with reconfigurable architecture is implemented in this study. This processor is a combination of a line buffer, controller units, as well as a reconfigurable and separable convolution module. The use of a reconfigurable architecture and separable convolution approach improves the flexibility and performance of the convolution processor. The reconfigurable and separable convolution array, which is the main component of the processor, can simultaneously execute convolution operation with different kernels, with a maximum kernel size of up to 24 × 24. Experimental results show that the maximum frames rate of the processor is approximately 194 frames per second (fps), which exceeds the real-time requirement. Synthesis results show that the processor occupies 13.39 mm 2 at a 204 MHz system clock and consumes a power of 419 mW at maximum kernel size at a 120 MHz system clock in SMIC 0.18 μm CMOS technology. Verification experiments on field programmable gate arrays (FPGAs) demonstrate that the processor is suitable for realtime image processing applications even for high-resolution images.

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Coarse-grained Dynamically Reconfigurable Processor for Vision Pre-Processing

Cited by 5 publications

References 14 publications

Resource-Efficient Image Buffer Architecture for Neighborhood Processors

Resource-Efficient Image Buffer Architecture for Neighborhood Processors

A Low Cost Structurally Optimized Design for Diverse Filter Types

Hardware Implementation of Reconfigurable 1D Convolution

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