Coarse Grained FPGA Overlay for Rapid Just-In-Time Accelerator Compilation

Abstract

Coarse-grained FPGA overlays built around the runtime programmable DSP blocks in modern FPGAs can achieve high throughput and improved scalability compared to traditional overlays built without detailed consideration of FPGA architecture. These overlays can be mapped to using higher level compilers, achieving fast compilation, software-like programmability and run-time management, and high-level design abstraction. OpenCL allows programs running on a host computer to launch accelerator kernels which can be compiled at run-time for a specific architecture, thus enabling portability. However, prohibitive hardware compilation times in traditional design flows mean that the tools cannot effectively use just-in-time (JIT) compilation or runtime performance scaling on FPGAs. We present a methodology for runtime compilation of dataflow graphs expressed as OpenCL kernels onto coarse-grained overlays. The methodology benefits from the high level of abstraction afforded by using the OpenCL programming model, while the mapping to the overlay significantly reduces compilation and load times. Key characteristics of this work include highly performant DSP-optimized functional units that scale to large overlays on modern devices and the ability to perform automatic resource-aware kernel replication up to the size of the overlay. We demonstrate place and route times orders of magnitude better than traditional HLS flows, even when running on an embedded processor in the Xilinx Zynq.

Fast flow cloud: A stream dataflow framework for cloud FPGA accelerator overlays at runtime

“…Section 6.1 presents the FPGA resources used by the FFC CGRA overlay. Section 6.2 compares the FFC mapping time to FPGA and DSP overlay approaches 11 . Section 6.3 evaluates the synthesis, compilation and reconfiguration time of FCC and three other approaches 4,6,11 .…”

“…Section 6.2 compares the FFC mapping time to FPGA and DSP overlay approaches 11 . Section 6.3 evaluates the synthesis, compilation and reconfiguration time of FCC and three other approaches 4,6,11 . Section 6.4 compares FFC performance in Gops/s to a time‐multiplexed overlay 7 .…”

“…The overlay is mapped once to the FPGA. Jain et al 11 propose a run‐time compilation of OpenCL kernels to a DSP block CGRA overlay. The target platform is an ARM processor of the embedded heterogeneous Zynq device.…”

“…Third, we improve the CGRA reconfiguration engine. Also, we compare the performance of the shared memory cache‐coherent HARPv2, AWS local memory F1 instance, a DSP time‐multiplexed overlay approach proposed in References 7,8,11, and an eight‐thread high‐performance XEON processor. Finally, the framework is open‐source for collaborative development and has clearly defined application programming interfaces (API) for future extensions.…”

“…Section 5 introduces the FFC tool, and highlights the main contributions. Section 6 shows the improvements in the mapping time, reconfiguration time, and performance achieved by FFC in comparison to other overlay‐based tools 6‐9,11 . Section 7 discusses related work on FPGA accelerator frameworks.…”