Cobalt Electrofill for Future Generations of Contacts and Interconnects

Spurlin, Tighe A.; Rigsby, Matthew A.; Brogan, Lee; Doubina, Natalia; Liu, Yihua; Opocensky, Edward C.; Jian, Zhou; Reid, Jonathan D.

doi:10.1109/cstic.2019.8755663

Cited by 4 publications

(2 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Intermetallic compounds (such as, Cu 2 Mg, AlNi, Al 3 Sc, AlCu, and Al 2 Cu) are proposed as candidate interconnected materials for advanced semiconductor devices [314][315][316][317]. The stoichiometric NiAl film with a thickness of 56 nm exhibits a resistivity of 13.9 µΩ cm after annealing at 600 • C. Additionally, different capping layers were tested to overcome the formation of metal surface oxides to achieve low resistivity [316].…”

Section: Metal Materials Interconnectmentioning

confidence: 99%

“…The resistivity of 24 nm Al 3 Sc thin film can reach 12.5 µΩ cm after post-deposition annealing at 500 • C. At a thickness of 20 nm and above, the conductivity of AlCu and Al 2 Cu films is better than that of Ru films, and the resistance of AlCu and Al 2 Cu films with a thickness of 28 nm is only 9.5 µΩ cm [314]. Meanwhile, Al 2 Cu exhibits low resistivity, excellent gap-filling performance, and good reliability in TDDB, EM and BTS [315]. Based on the above series of good properties, Al 2 Cu may become an alternative to Cu [314].…”

Section: Metal Materials Interconnectmentioning

confidence: 99%

See 1 more Smart Citation

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Radamson,

Miao,

Zhou

et al. 2024

Nanomaterials

View full text Add to dashboard Cite

After more than five decades, Moore’s Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

show abstract