To design highly parallel digital circuits such as a n adder and a multiplier, it is dificult to find the optim a l code assignmen,t in the non-linear digital system. O n the other hand, the use of the linear concept in digital systems seems t o be very attractive because analytical methods can be utilised. For u n a r y operations, the design method of locally computable circuits have been discussed. In this paper, w e propose a n e w design method of highly parallel multiple-valued linear digital circuits f o r I;-ary operations using the concept of identification of input-output graphs b y th.e introduction of multiplicated redundant symbols.