Proceedings of the 10th Workshop on Optimizations for DSP and Embedded Systems 2013
DOI: 10.1145/2443608.2443612
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Code generation for an application-specific VLIW processor with clustered, addressable register files

Abstract: Modern compilers integrate recent advances in compiler construction, intermediate representations, algorithms and programming language front-ends. Yet code generation for application-specific architectures benefits only marginally from this trend, as most of the effort is oriented towards popular general-purpose architectures. Historically, non-orthogonal architectures have relied on custom compiler technologies, some retargettable, but largely decoupled from the evolution of mainstream tool flows.Very Long In… Show more

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“…The highly specialized micro architecture has a 10 stage pipeline and achieves 400 MHz in a 65 nm process. In [4] an LLVM backend is presented for Mephisto.…”
Section: Introduction a N D R E L A T E D W O R Kmentioning
confidence: 99%
“…The highly specialized micro architecture has a 10 stage pipeline and achieves 400 MHz in a 65 nm process. In [4] an LLVM backend is presented for Mephisto.…”
Section: Introduction a N D R E L A T E D W O R Kmentioning
confidence: 99%