Code Synthesis for Dataflow-Based Embedded Software Design

Su, Zhuo; Wang, Dongyan; Yang, Yixiao; Jiang, Yu; Chang, Wanli; Fang, Liming; Li, Wen; Sun, Jun

doi:10.1109/tcad.2021.3055487

Cited by 10 publications

(2 citation statements)

References 26 publications

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“…They cannot overlap, obeying the execution sequence shown in (18). M axvalue is a very large value, and the inequality should be satisfied when o ik is 1. o ik is calculated using the inequality (19), which means that if both r ik and j y ijk are 1, o ik is 1; otherwise, it is 0. One-step ILP may suffer from a long solver time because its objective function and constraints are complex.…”

Section: A Formulation Of One-step Ilpmentioning

confidence: 99%

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Task Mapping and Scheduling on RISC-V MIMD Processor With Vector Accelerator Using Model-Based Parallelization

Wu,

Kumano,

Marume

et al. 2024

IEEE Access

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In this paper, we propose a model-based workflow to generate parallel code on a multiple instruction stream, multiple data stream (MIMD) processor with vector accelerator (MIMDV) from a Simulink model. Solving data-and task-parallelism is crucial during this process. For data parallelism, a RISC-V Simulink library written in vector codes was prepared for blocks with sufficient vector or matrix calculations. Moreover, large inputs can be divided, which means that tasks can be executed simultaneously using multiple cores. For task parallelism, integer linear programming (ILP) was designed to deploy tasks on scalar processing elements (SPEs) and a vector processing element (VPE) of MIMDV. The use of a vector library for a task and the number of SPEs a task uses were determined. To reduce the overhead, synchronization is realized by barrier wait, and execution is divided into multiple time intervals called layer. We propose a novel one-step ILP that accurately minimizes the parallel time of such a situation. Furthermore, we propose a two-step ILP to achieve reasonable performance in practical time. One step is SPE mapping, and the other is layer scheduling. We tested our methods using random task graphs and real-world applications on DR1000C, a type of RISC-V MIMD processor with a vector accelerator.

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Section: A Formulation Of One-step Ilpmentioning

confidence: 99%

“…Except the MATLAB/Simulink, [19] generated efficient C and Java codes using DFSynth, and actors are divided into multiple layers in schedule analysis. [21] generated parallel codes from Lustre or Scade models.…”

Section: Related Workmentioning

confidence: 99%