Codesign of ${K}$ a-Band Integrated GaAs PIN Diodes Limiter and Low Noise Amplifier

Abstract

In this paper, a novel concurrent design of integrated PIN-diode based limiter and low noise amplifier (LNA) is presented for Ka-band MMICs fabricated using a combined PIN/0.15-µm-pHEMT technology. To improve the small-signal performance and the power-handling capability of the limiter-LNA, the improvement of the PIN-limiter circuit structure and the survivability of the LNA network are proposed. In addition, the total chip area is 2.5 mm × 1.2 mm with an equalizer integrated on chip behind the limiter-LNA to improve the bandwidth with a minimum impact on overall NF. The measurements show that the proposed limiter-LNA with only two-stage limiter structure tolerates up to 38 dBm continuous wave (CW) input power without failure, and the average gain and the noise figure for the limiter-LNA are 17 dB and 2.2-2.6 dB, respectively, on the 30-38 GHz frequency bandwidth. INDEX TERMS GaAs pHEMT, integrated limiter low noise amplifier (LNA), MMIC, noise figure (NF), PIN diode.

A compact Ka‐band limiter‐low noise amplifier MMIC with high power capability

“…The limiter-LNA in this paper has the highest input-power capability and the smallest chip area among the Ka-band limiter-LNA MMICs ever reported. 4,9 2 | LIMITER-LNA MMIC DESIGN…”

“…In the limiter-LNA F I G U R E 1 Complete schematic of the proposed limiter-LNA MMIC MMICs reported to date, the interstage transmission lines of the limiter are conventionally set to about 30°-40°due to the chip size limit. 9,10 This method results in a poor impedance transformation performance from the clean-up stage to the coarse stage, which leads to a lower power handling capability of the limiter-LNA. To improve the impedance transformation performance, in this study, the characteristic impedance of the interstage transmission line is increased to enlarge the series inductance, and a capacitor C T is introduced to increase the shunt capacitance; as shown in Figure 3, this capacitor C T and two shorter transmission lines L T together form an impedance transformer.…”

“…From the above study, it can be seen that the limiter-LNA MMIC proposed in this paper can achieve higher power-handling capability, better small-signal performance, and smaller chip area compared with the existing methods. 9,10 To achieve a total small-signal gain of 20 dB, a threestage common-source LNA structure is employed. Source degeneration is used through a short stub to improve the noise performance and the input matching, simultaneously.…”

“…In recent years, limiter‐LNA MMICs using the PIN/GaAs‐pHEMT process are reported for high power‐capability, high integration, and low cost. Yang et al 9 report a Ka‐band 38 dBm PIN diode limiter‐LNA MMIC with 2.5 mm × 1.2 mm chip area; however, the chip area is very large, and the power‐handling capability also needs to be improved for high power and high mobility millimeter‐wave radar applications.…”

First Demonstration of L-Band High-Power Limiter with GaN Schottky Barrier Diodes (SBDs) Based on Steep-Mesa Technology

“…A diode limiter prevents the damage of sensitive receiver components by allowing RF signals below a certain threshold to pass through, but larger signals exceeding the threshold are attenuated [3]. The development of modern RF receivers requires a high-performance diode limiter [4] that can operate in a wide bandwidth and at a high-input power level with compactness, easy integration and low cost. Many studies have been carried out on Si-based diode limiters in recent years [5][6][7]; however, they showed scant room for further improvement as the silicon reached its theoretical limitations.…”