Coherence Maintenances to realize an efficient parallel processing for a Cache Memory with Synchronization on a Chip-Multiprocessor

2016

VLSI Design

This work reports an effective design of cache system for Chip Multiprocessors (CMPs). It introduces built-in logic for verification of cache coherence in CMPs realizing directory based protocol. It is developed around the cellular automata (CA) machine, invented by John von Neumann in the 1950s. A special class of CA referred to as single length cycle 2-attractor cellular automata (TACA) has been planted to detect the inconsistencies in cache line states of processors’ private caches. The TACA module captures coherence status of the CMPs’ cache system and memorizes any inconsistent recording of the cache line states during the processors’ reference to a memory block. Theory has been developed to empower a TACA to analyse the cache state updates and then to settle to an attractor state indicating quick decision on a faulty recording of cache line status. The introduction of segmentation of the CMPs’ processor pool ensures a better efficiency, in determining the inconsistencies, by reducing the number of computation steps in the verification logic. The hardware requirement for the verification logic points to the fact that the overhead of proposed coherence verification module is much lesser than that of the conventional verification units and is insignificant with respect to the cost involved in CMPs’ cache system.

Section: Introductionmentioning

confidence: 99%

A Cache System Design for CMPs with Built-In Coherence Verification

2016

VLSI Design

“…Therefore, maintaining coherency of shared data [8] in CMPs is of utmost necessity. The schemes ensuring coherency in CMPs through frequent communication, are reported in [2], [3], [4] & [5]. This communication among L1 caches affects the system performance and the energy usage [1].…”

Section: Introductionmentioning

confidence: 99%

A Protocol Independent Test Design for Quick Determination of Incoherency in CMPs' Cache

2013 4th International Conference on Intelligent Systems, Modelling and Simulation

2013

The data coherence in the cache systems of CMPs (Chip Multi-Processors) is to be more accurate and reliable. The conventional solutions for verification of cache coherence targeting small systems are not so effective in CMPs. The CMPs cache system further demands a protocol independent test logic. In this work, we propose an effective solution to the issue through introduction of highly efficient test logic (fault detection unit). The design is developed around a special class of Cellular Automata (CA) referred to as the SACA (single length single cycle attractor cellular automata). The SACA is introduced to identify the inconsistencies in cache line states of processors' private caches catering the MSI/MESI/MOESI protocols. The SACA theory developed for the design enables protocol independent verification hardware logic to realize quick decision on the accurate cache coherency in CMPs.

“…The schemes ensuring coherency in CMPs with thousands of cores, through frequent communication along the global wires, are reported in [3], [4], [5], [6], [7]. This communication among the L1 caches seriously affects the system performance as well as the energy usage.…”

Section: Introductionmentioning

confidence: 99%

An Efficient Test Design for Verification of Cache Coherence in CMPs

2011 IEEE Ninth International Conference on Dependable, Autonomic and Secure Computing

2011

The data coherence in the cache systems of CMPs with thousands of processors are to be more accurate and reliable. This work proposes an effective solution to address this issue through introduction of highly efficient test logic with the cache controller. It is based on the modular structure of Cellular Automata (CA) and a special class of CA referred to as the SACA (single length single cycle attractor CA) has been introduced to identify the inconsistencies in cache line states of the processors' private caches. The hardware implementation of the proposed test logic can ensure quick verification of cache inconsistencies in CMPs. The proposed design eliminates the requirement of huge storage as well as the complex data structures commonly used to verify the data coherency in a multiprocessor system.