Cointegration of the TFT-Type AND Flash Synaptic Array and CMOS Circuits for a Hardware-Based Neural Network

Park, Min-Kyu; Kang, Won-Mook; Koo, Ryun-Han; Kim, Jeonghyun; Hwang, Joon; Bae, Jong-Ho; Kim, Jae‐Joon; Lee, Jong‐Ho

doi:10.1109/ted.2022.3220726

IEEE Trans. Electron Devices

2023

DOI: 10.1109/ted.2022.3220726

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Cointegration of the TFT-Type AND Flash Synaptic Array and CMOS Circuits for a Hardware-Based Neural Network

Min-Kyu Park

Won-Mook Kang

Ryun-Han Koo

et al.

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2024

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Cited by 8 publications

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Lateral Migration‐based Flash‐like Synaptic Device for Hybrid Off‐chip/On‐chip Training

Park,

Hwang,

Lee

et al. 2024

Adv Elect Materials

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An increase in the demand for artificial intelligence is leading to advanced research in the field of neuromorphic systems, which imitate human brain functions with the hope of increasing computational speed and lowering power consumption. Especially, the development of energy‐efficient and reliable synaptic devices is critical as synapses are fundamental building blocks of neuromorphic systems. In this study, by adjusting the charge injection pathway of conventional flash memory devices, a lateral migration‐based synaptic device is proposed. Using the efficient program/erase method, the proposed device is operable at a significantly low voltage while maintaining formidable retention and endurance characteristics. Furthermore, an efficient hybrid off‐chip/on‐chip training method using the proposed device is presented. The results demonstrate a variation‐robust neuromorphic system, indicating the superiority of the proposed device.

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Lateral Migration‐based Flash‐like Synaptic Device for Hybrid Off‐chip/On‐chip Training

Park,

Hwang,

Lee

et al. 2024

Adv Elect Materials

Self Cite

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Multifunctional In‐Memory Analog‐to‐Digital Converter for Next‐Gen Compute‐in‐Memory Systems

Im,

Ko,

Hwang

et al. 2024

Advanced Intelligent Systems

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Compute‐in‐memory (CIM) technology based on emerging nonvolatile memories (NVMs) has shown promise in enhancing artificial intelligence applications by integrating computation directly within NVM arrays. However, the efficiency of CIM systems is often curtailed by the substantial overhead that is caused by traditional complementary metal‐oxide‐semiconductor (CMOS)‐based analog‐to‐digital converters (ADCs). Here, we report an in‐memory ADC (IMADC) that leverages NVMs to perform the dual functionalities of reference generation and voltage comparison, effectively minimizing the area occupancy and energy consumption, is reported. The IMADC not only significantly outperforms traditional ADCs but also enables the inherent processing of nonlinear activation functions such as the sigmoid function, which is required for neural networks. The IMADC‐based CIM system achieves software‐comparable accuracy in CIFAR‐10 image classification on the VGG‐9 network. The IMADC exhibits significantly reduced area occupancy (45 μm2) and energy consumption (29.6 fJ) compared to conventional CMOS‐based ADCs. The IMADC, compatible with various types of NVMs, demonstrates significant potential for enhancing the efficiency of CIM systems in terms of area occupancy and energy consumption.

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Charge-trap synaptic device with polycrystalline silicon channel for low power in-memory computing

Park,

Hwang,

Kim

et al. 2024

Sci Rep

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Processing-in-memory (PIM) is gaining tremendous research and commercial interest because of its potential to replace the von Neumann bottleneck in current computing architectures. In this study, we implemented a PIM hardware architecture (circuit) based on the charge-trap flash (CTF) as a synaptic device. The PIM circuit with a CT memory performed exceedingly well by reducing the inference energy in the synapse array. To evaluate the image recognition accuracy, a Visual Geometry Group (VGG)-8 neural network was used for training, using the Canadian Institute for Advanced Research (CIFAR)-10 dataset for off-chip learning applications. In addition to the system accuracy for neuromorphic applications, the energy efficiency, computing efficiency, and latency were closely investigated in the presumably integrated PIM architecture. Simulations that were performed incorporated cycle-to-cycle device variations, synaptic array size, and technology node scaling, along with other hardware-sense considerations.

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Cointegration of the TFT-Type AND Flash Synaptic Array and CMOS Circuits for a Hardware-Based Neural Network

Cited by 8 publications

References 18 publications

Lateral Migration‐based Flash‐like Synaptic Device for Hybrid Off‐chip/On‐chip Training

Lateral Migration‐based Flash‐like Synaptic Device for Hybrid Off‐chip/On‐chip Training

Multifunctional In‐Memory Analog‐to‐Digital Converter for Next‐Gen Compute‐in‐Memory Systems

Charge-trap synaptic device with polycrystalline silicon channel for low power in-memory computing

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