Collaborative gate implementation selection and adaptivity assignment for robust combinational circuits

Abstract

Adaptive design is a power-efficient approach to variation resilience in VLSI circuits. However, its implementation, especially that of fine-grained adaptivity, can easily result in large overhead. Although numerous previous works have demonstrated the effectiveness of adaptive design, very few works have emphasized its overhead control. In order to make adaptive design a truly practical approach, we develop a method that systematically optimizes adaptivity assignment with consideration of overhead reduction. At the same time, a variability aware gate implementation selection technique is investigated and applied in conjunction with the adaptivity assignment. Experimental results on benchmark circuits indicate that our approach can greatly decrease adaptivity overhead while satisfy performance and robustness constraints.

Proximity Optimization for Adaptive Circuit Design

“…In this work, we propose a balanced approach: cell clustering with consideration of both timing and spatial proximity. [11], which decides if to assign adaptivity to each block and simultaneously performs gate sizing.…”

“…Unlike the original Lloyd's algorithm, which is based on Euclidean distance, we use Manhattan distance to match the layout convention in VLSI circuits. The value of K is decided empirically [11]. Moreover, we allow K to be changed according to clustering results.…”

“…Adaptivity comes with area overhead due to sensor and tuning circuit. The adaptivity assignment tool we use [11] has the following inputs: circuit G composed by clusters C = {C 1 , C 2 , ...}, timing yield constraint Υ, and adaptivity area constraint Ω. The algorithm iteratively assigns or de-assigns adaptivity for a cluster.…”

“…The wirelength is evaluated according to half-perimeter of net bounding boxes. The last step gate sizing and adaptivity assignment uses the method of [11].…”