CoLT: Coalesced Large-Reach TLBs

Pham, Binh Thai; Vaidyanathan, Viswanathan; Jaleel, Aamer; Bhattacharjee, Abhishek

doi:10.1109/micro.2012.32

Cited by 159 publications

(128 citation statements)

References 25 publications

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“…We then estimate the reduction in TLB-miss-handling time with direct-segment using a linear model. This is similar to a recent work on coalesced TLB by Pham et al [36]. More specifically, we find the fraction of total TLB misses that fall in the primary region mapped with a direct segment using the methodology described above.…”

Section: Primary Region/direct Segmentsupporting

confidence: 90%

“…Zhang et al proposed an intermediate address space between the virtual and physical addresses, under which physical address translation is only required on a cache miss [50]. Recently, Pham et al [36] proposed hardware support to exploit naturally occurring contiguity in virtual to physical address mapping to coalesce multiple virtual-tophysical page translations into single TLB entries.…”

Section: Related Workmentioning

confidence: 99%

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Efficient virtual memory for big memory servers

Basu

Gandhi

Chang

et al. 2013

SIGARCH Comput. Archit. News

106

188

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Our analysis shows that many "big-memory" server workloads, such as databases, in-memory caches, and graph analytics, pay a high cost for page-based virtual memory. They consume as much as 10% of execution cycles on TLB misses, even using large pages. On the other hand, we find that these workloads use read-write permission on most pages, are provisioned not to swap, and rarely benefit from the full flexibility of page-based virtual memory.To remove the TLB miss overhead for big-memory workloads, we propose mapping part of a process's linear virtual address space with a direct segment, while page mapping the rest of the virtual address space. Direct segments use minimal hardware-base, limit and offset registers per core-to map contiguous virtual memory regions directly to contiguous physical memory. They eliminate the possibility of TLB misses for key data structures such as database buffer pools and in-memory key-value stores. Memory mapped by a direct segment may be converted back to paging when needed.We prototype direct-segment software support for x86-64 in Linux and emulate direct-segment hardware. For our workloads, direct segments eliminate almost all TLB misses and reduce the execution time wasted on TLB misses to less than 0.5%.

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Section: Primary Region/direct Segmentsupporting

confidence: 90%

Section: Related Workmentioning

confidence: 99%

Efficient virtual memory for big memory servers

Basu

Gandhi

Chang

et al. 2013

SIGARCH Comput. Archit. News

106

188

View full text Add to dashboard Cite

show abstract

“…1. Multipage mappings use one TLB entry to map multiple pages (e.g., [8][9][10][11][12][13][14][15][16] pages per entry) [38,39,47]. Mapping multiple pages per entry increases TLB reach by a small fixed amount, but has alignment restrictions, and still leaves TLB reach far below modern gigabyte-to-terabyte physical memory sizes.…”

Section: Introductionmentioning

confidence: 99%

“…Section 9 discusses related work more generally. Multipage Mapping approaches, such as sub-blocked TLBs [47], CoLT [39] and Clustered TLBs [38], pack multiple Page multiple of translations (e.g., [8][9][10][11][12][13][14][15][16] per entry, which limits their potential to reduce page-walks for large working sets.…”

Section: Introductionmentioning

confidence: 99%

Redundant memory mappings for fast access to large memories

Karakostas

Gandhi

Ayar

et al. 2015

Proceedings of the 42nd Annual International Symposium on Computer Architecture

137

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Page-based virtual memory improves programmer productivity, security, and memory utilization, but incurs performance overheads due to costly page table walks after TLB misses. This overhead can reach 50% for modern workloads that access increasingly vast memory with stagnating TLB sizes.To reduce the overhead of virtual memory, this paper proposes Redundant Memory Mappings (RMM), which leverage ranges of pages and provides an efficient, alternative representation of many virtual-to-physical mappings. We define a range be a subset of process's pages that are virtually and physically contiguous. RMM translates each range with a single range table entry, enabling a modest number of entries to translate most of the process's address space. RMM operates in parallel with standard paging and uses a software range table and hardware range TLB with arbitrarily large reach. We modify the operating system to automatically detect ranges and to increase their likelihood with eager page allocation. RMM is thus transparent to applications.We prototype RMM software in Linux and emulate the hardware. RMM performs substantially better than paging alone and huge pages, and improves a wider variety of workloads than direct segments (one range per program), reducing the overhead of virtual memory to less than 1% on average.

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“…Pham et al [61] propose CoLT (Figure 2.5b) to exploit PTEs spatial locality to aggregate data and increase TLB hit ratio, but without the overheads of superpaging, such as complex algorithms and inflated I/O traffic. Therefore, while conventional TLB entries correspond to a single PTE, a CoLT entry maps to a region composed by dozens of contiguous, spatially-local PTEs.…”

Section: Exploiting Spatial Localitymentioning

confidence: 99%

Design of Efficient TLB-based Data Classification Mechanisms in Chip Multiprocessors

García¹

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AcknowledgmentCuatro años de esfuerzo dan para mucho. Echándo la vista atrás, muchas son las personas que me han apoyado, muchos los que me han escuchado. Gracias a todos.A Ramón y Lola. Sin ellos, sin su apoyo y su amor, no habría llegado hasta aquí. Sin su inspiración no habría siquiera empezado el camino. Ellos plantaron la semilla de la curiosidad, tan necesaria para superar la frustración y las dificultades a las que todo investigador tiene que enfrentar en su camino.A Víctor. Hermano y amigo. El espejo en el que me miro. Me has dado fuerza en cada etapa de mi vida. Gracias por todo. Habrá que pensar una buena ruta en bici para celebrarlo.A Carla. Por su paciencia, por su ayuda, por respaldarme cuando lo he necesitado. Siempre me has animado a seguir adelante y has permanecido a mi lado en cada etapa del doctorado. Más que eso, eres uno de los pilares principales de mi vida.A Salomé, Eloy y Sergio. Por quererme y aceptarme como uno más de la familia. Realmente yo lo siento del mismo modo. Gracias.A mis amigos. Samuel, Eduardo, Manolo. Ya sea jugando a algún juego, organizándo viajes juntos, o saliendo de fiesta o a tomar algo, siempre habéis estado ahí, siendo partícipes de mis logros y mis frustraciones. Tanto como yo de las vuestras. Y espero que siga siendo así por muchos, muchos años.Allá por 2007 empezaba mi andadura por la universidad, hace ya diez años.Ésta ha sido mi segunda casa, y le debo mucho. Y tengo muchos que agradecer también a toda la gente que he conocido en este etapa. Incluyendoéstaúltima fase en el Grupo de Arquitecturas Paralelas.Por supuesto y ante todo a mis directores, Alberto, Antonio y Maria Engracia. Me habéis guiado e inspirado, desafiado y ayudado en cada etapa de mi doctorado. Vuestra paciencia y esfuerzo han sido claves para la consecución de este trabajo. He aprendido mucho durante estos años. No sólo en materia de arquitectura de computadores, sino también en investigación científica; a amarla, a observar los pequeños detalles, a analizar los datos y entender qué esta ocurriendo para así poder seguir avanzando. Ellos han cambiado mi vida, profesional y personal, para siempre.A Núria, Salva y Eduardo. No nos vemos tanto como antes, nuestras vidas, sus obligaciones, nos alejan. Pero aún nos quedarán esas tardes de cervezas para ponernos al día. Siempre.A mis compañeros de laboratorio. José Vicente, José María, Migue, Vicent, Joan, Fran, Javi, Roberto, Carlos, Santi, y un largo etcétera. A los que se fueron, Knut, Mario, Crispín. Tantos y tantos. A todos os debo algo. Lo que ha unido el BoardGameArena que no lo separen nuestras exitosas carreras en el extranjero, como un tren de mercancías desbocado y sin frenos. Y por supuesto a Ricardo. El verdadero pilar del laboratorio, en lo técnico y en lo personal. Tu increible paciencia y dedicación te hacen pieza central del trabajo de todos nosotros en el grupo.

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CoLT: Coalesced Large-Reach TLBs

Abstract: Translation Lookaside Buffers (TLBs)

Cited by 159 publications

References 25 publications

Efficient virtual memory for big memory servers

Efficient virtual memory for big memory servers

Redundant memory mappings for fast access to large memories

Design of Efficient TLB-based Data Classification Mechanisms in Chip Multiprocessors

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