Combination of Circuit and Full Wave Analysis for Pre-Matched Multifinger FET

Cetiner, Bedri A.; Coccioli, R.; Housmand, B.; Itoh, T.

doi:10.1109/euma.2000.338658

Cited by 11 publications

(2 citation statements)

References 8 publications

(9 reference statements)

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“…This is represented by C N gd ·N f in (2). By the same token, the capacitive coupling between substrate-contact ring and drain fingers generates parasitic capacitance, which is represented by C N ds ·N f in (3).…”

Section: Extrinsic Element Scaling Rulesmentioning

confidence: 99%

“…Since no straightforward scaling rules exist for the extrinsic networks, there have been researches to employ a Full-Wave Electo-Magnetic (FW-EM) simulation to extract layoutdependent extrinsic parameters [2]- [4]. However, these works have so far been limited to GaAs HEMT devices, and few attempts have been made to build a scalable CMOS FET model including the layout-dependent extrinsic elements.…”

Section: Introductionmentioning

confidence: 99%

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Scalable small-signal modeling of RF CMOS FET based on 3-D EM-based extraction of parasitic effects

Jung

Choi

Kwon

2009

2009 IEEE MTT-S International Microwave Symposium Digest

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An accurate scalable RF CMOS model applicable to high frequencies is developed using 3-D EM-based extraction of parasitic elements for the first time. Due to multi-metal layers, vertical interconnects, substrate loss and substrate-contact rings, the extrinsic parasitic network of CMOS FET is more complicated than GaAs FET's and does not follow simple scaling rules. A pair of dummy patterns with different reference planes and 3-D EM simulations are sequentially used to extract the pads, vertical interconnects and extrinsic parasitic network. A new scaling rule is proposed for the layout-dependent extrinsic network parameters. A complete scalable RF CMOS model is validated by comparing the predicted and measured Sparameters of the scaled devices from a family of 0.18 μm CMOS FET's up to 50GHz, which resulted in less than 2% error. The method is useful in choosing the optimum device geometry for a given circuit application.

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Section: Extrinsic Element Scaling Rulesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%