2021
DOI: 10.1021/acsaelm.1c00689
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Combination of Gate-Stack Process and Cationic Composition Control for Boosting the Performance of Thin-Film Transistors Using In–Ga–Zn–O Active Channels Prepared by Atomic Layer Deposition

Abstract: Combination impacts of controlling the gate-stack process conditions and the indium contents of In–Ga–Zn–O (IGZO) channels prepared by atomic layer deposition (ALD) were investigated to strategically enhance the device performance including carrier mobility for ALD IGZO thin-film transistors (TFTs). The ALD cyclic ratios (triethyl indium/In–Ga precursor/diethyl zinc) were varied to 0:2:2, 2:2:2, and 4:2:2 for the formation of IGZO channels, which correspond to the In/Ga ratios of 0.3, 1.0, and 2.0. While the d… Show more

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Cited by 19 publications
(4 citation statements)
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“…Using table 1, we determined that studies of indium-based oxide semiconductors have greatly increased since 2021. Not only binary In 2 O 3 [42][43][44][45][46][47][48][49], but also a ternary as IGO [59][60][61][62], IZO [62,63], In-Al-O (IAO) [64,65] and ITO [66], quaternary as IGZO [4,30,[71][72][73][74][75][76][77][78][79][80], ITAO [81,82], and ITGO [83] have been introduced. Also, compared to other materials in table, the precursors for indium oxide are variously used.…”
Section: Chemical Reaction and Film Propertiesmentioning
confidence: 99%
“…Using table 1, we determined that studies of indium-based oxide semiconductors have greatly increased since 2021. Not only binary In 2 O 3 [42][43][44][45][46][47][48][49], but also a ternary as IGO [59][60][61][62], IZO [62,63], In-Al-O (IAO) [64,65] and ITO [66], quaternary as IGZO [4,30,[71][72][73][74][75][76][77][78][79][80], ITAO [81,82], and ITGO [83] have been introduced. Also, compared to other materials in table, the precursors for indium oxide are variously used.…”
Section: Chemical Reaction and Film Propertiesmentioning
confidence: 99%
“…In the top-gate structure, wet chemical processes involved in this photolithography can affect the characteristics of the TFT, because the IGZO top surface becomes the channel interface of the TFT later [ 14 ]. Several papers have reported TFT methodologies that perform photolithographic patterning after continuous deposition of gate dielectrics as a protective layer (PL) on IGZO to avoid the top surface being exposed to these chemicals [ 15 , 16 , 17 ]. The consecutive deposition of the gate dielectric PL on IGZO can prevent chemical damage on the channel surface, but since additional gate dielectrics must be deposited again after forming an active island pattern, the entire TFT fabrication process becomes complicated.…”
Section: Introductionmentioning
confidence: 99%
“…The current research on a-IGZO TFT is mainly focused on the following aspects: adopting semiconductor layer doping process to improve device performance and stability [14], adopting new protective layer materials to improve device stability [15], developing new electrode materials [16], investigating the mechanism of device electrical stability [17], adjusting device structure and device applications [18][19]. Among them, for the simulation of a-IGZO TFT device performance, the traditional physics-based modeling method is mainly done by modeling the device and scanning the corresponding physical quantity parameters by TCAD simulation software, but the method is very time-consuming and tedious, and it is difficult to keep up with the development of a-IGZO TFT.…”
Section: Introductionmentioning
confidence: 99%