Combinational and Sequential Equivalence Checking

Kuehlmann, Andreas; Eijk, C.A.J. van

doi:10.1007/978-1-4615-0817-5_13

Cited by 24 publications

(14 citation statements)

References 36 publications

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“…Formal Equivalence Checking is a technique used to formally prove that two models M and M exhibit the same observable behavior [19]. This is achieved by comparing the input and the output behavior of the two models.…”

Section: Equivalence Checkingmentioning

confidence: 99%

Mutation-Based Test Case Generation for Simulink Models

Brillout

Mazzucchi

et al. 2010

Lecture Notes in Computer Science

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Abstract. The Matlab/Simulink language has become the standard formalism for modeling and implementing control software in areas like avionics, automotive, railway, and process automation. Such software is often safety critical, and bugs have potentially disastrous consequences for people and material involved. We define a verification methodology to assess the correctness of Simulink programs by means of automated test-case generation. In the style of fault-and mutation-based testing, the coverage of a Simulink program by a test suite is defined in terms of the detection of injected faults. Using bounded model checking techniques, we are able to effectively and automatically compute test suites for given fault models. Several optimisations are discussed to make the approach practical for realistic Simulink programs and fault models, and to obtain accurate coverage measures.

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Section: Equivalence Checkingmentioning

confidence: 99%

Mutation-Based Test Case Generation for Simulink Models

Brillout

Mazzucchi

et al. 2010

Lecture Notes in Computer Science

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“…In sequential equivalence checking the perfect trace equivalence between clocked circuits is analysed; see [18] or [20] for an overview. Lu and Cheng [23] present an approach based on inferred invariants, conditional or relational equivalence are not considered.…”

Section: Related Workmentioning

confidence: 99%

Regression Verification for Programmable Logic Controller Software

Beckert

Ulbrich

Vogel‐Heuser

et al. 2015

Formal Methods and Software Engineering

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Abstract. Automated production systems are usually driven by Programmable Logic Controllers (PLCs). These systems are long-living -yet have to adapt to changing requirements over time. This paper presents a novel method for regression verification of PLC code, which allows one to prove that a new revision of the plant's software does not break existing intended behavior. Our main contribution is the design, implementation, and evaluation of a regression verification method for PLC code. We also clarify and define the notion of program equivalence for reactive PLC code. Core elements of our method are a translation of PLC code into the SMV input language for model checkers, the adaptation of the coupling invariants concept to reactive systems, and the implementation of a toolchain using a model checker supporting invariant generation. We have successfully evaluated our approach using the Pick-and-Place Unit benchmark case study.

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“…A multi-block structure is considered as a logical circuit containing, along with logical elements (AND, OR, and NOT), special signal merging elements for which the implemented functions are determined in terms of ternary logic. Formulas (2) are used in the construction of permissible CNF for logical elements, and the specially introduced signal merging condition is used for the signal merging elements.…”

Section: A Formation Of the Permissible Cnf For An Isf Systemmentioning

confidence: 99%

“…Today, verification is a bottleneck in the overall VLSI design cycle as it consumes up to 70% of design efforts ( [1], [2]). Unfortunately, the capabilities of verification tools have noticeably yielded to the capabilities of design systems, to say nothing of the technological achievements of the semiconductor industry.…”

Section: Introductionmentioning

confidence: 99%

SAT-based approaches to verification of logical descriptions with functional indeterminacy

Черемисинова

2013

Ninth International Conference on Computer Science and Information Technologies Revised Selected Papers

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The problem under discussion is to check whether a given system of incompletely specified Boolean functions is implemented by a logical description that is represented by a system of connected blocks each of which is specified by a system of completely or incompletely specified Boolean functions. SATbased verification approaches are considered which formulate the verification problem as checking satisfiability of a conjunctive normal form. The results of investigation of SATbased verification methods are given.Keywords-Computer-aided design, formal verification, satisfiabilty of a conjunctive normal.

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Combinational and Sequential Equivalence Checking

Cited by 24 publications

References 36 publications

Mutation-Based Test Case Generation for Simulink Models

Mutation-Based Test Case Generation for Simulink Models

Regression Verification for Programmable Logic Controller Software

SAT-based approaches to verification of logical descriptions with functional indeterminacy

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