Combinatorial Register Allocation and Instruction Scheduling

Abstract

This paper introduces a combinatorial optimization approach to register allocation and instruction scheduling, two central compiler problems. Combinatorial optimization has the potential to solve these problems optimally and to exploit processor-specific features readily. Our approach is the first to leverage this potential in practice: it captures the complete set of program transformations used in state-of-the-art compilers, scales to mediumsized functions of up to 1000 instructions, and generates executable code. This level of practicality is reached by using constraint programming, a particularly suitable combinatorial optimization technique. Unison, the implementation of our approach, is open source, used in industry, and integrated with the LLVM toolchain.An extensive evaluation confirms that Unison generates better code than LLVM while scaling to mediumsized functions. The evaluation uses systematically selected benchmarks from MediaBench and SPEC CPU2006 and different processor architectures (Hexagon, ARM, MIPS). Mean estimated speedup ranges from 1.1% to 10% and mean code size reduction ranges from 1.3% to 3.8% for the different architectures. A significant part of this improvement is due to the integrated nature of the approach. Executing the generated code on Hexagon confirms that the estimated speedup results in actual speedup. Given a fixed time limit, Unison solves optimally functions of up to 946 instructions, nearly an order of magnitude larger than previous approaches.The results show that our combinatorial approach can be applied in practice to trade compilation time for code quality beyond the usual compiler optimization levels, identify improvement opportunities in heuristic algorithms, and fully exploit processor-specific features. This paper is partially based on preliminary work presented at the Principles and Practice of Constraint Programming (2012) [20]; Languages, Compilers, and Tools for Embedded Systems (2014) [21]; and Compiler Construction (2016) [22] conferences. Compared to the preliminary work, this paper is completely restructured and rewritten, completes the combinatorial model with rematerialization, proposes extensions to capture additional program transformations and processor-specific features, and contributes a more exhaustive evaluation. Additions to the evaluation include more benchmarks and processors, evidence of the fundamental benefit of the integrated approach, an in-depth study of scalability, and actual execution measurements.

Constraint-Based Software Diversification for Efficient Mitigation of Code-Reuse Attacks

“…Implementation. DivCon is implemented as an extension of Unison [6], and is available at https://github.com/romits800/divcon. Unison implements two backend transformations: instruction scheduling and register allocation.…”

Development of DSL Compilers for Specialized Processors

“…The practical applicability of the developed methods and algorithms for automating code generation for DSL compilers for specialized processors is confirmed by the experimental evaluation of the created JC compiler on a set of applications. NOLTIS [16], PBQP [17], CP [18] SAT [19], ILP [20], CP [21] Graph coloring [22], puzzle method [23], ILP [24], PBQP [25] ILP [26] ILP [27], CP [28] ILP [29]…”

Accelerating the Development of DSL Compilers for Specialized Processors

“…Планирование команд Распределение регистров NOLTIS [16], PBQP [17], CP [18] SAT [19], ЦЛП [20], CP [21] Раскраска графа [22], метод головоломок [23], ЦЛП [24], PBQP [25] ЦЛП [26] ЦЛП [27], CP [28] ЦЛП [29]…”