Combined Distributed Shared-Buffered and Diagonally-Linked Mesh Topology for High-Performance Interconnect

Abstract

Networks-on-Chip (NoCs) have become the de-facto on-chip interconnect for multi/manycore systems. A typical NoC router is made up of buffers used to store packets that are unable to advance to their desired destination. However, buffers consume significant power/area and are often underutilized, especially in cases of applications with non-uniform traffic patterns thus leading to performance degradation for such applications. To improve network performance, the Roundabout NoC (R-NoC) concept is considered. R-NoC is inspired by real-life multi-lane traffic roundabouts and consists of lanes that are shared by multiple input/output ports to maximize buffering resource utilization. R-NoC relies on router-internal adaptive routing that decides the lane path based on back pressure. Back pressure makes it possible to assess lane utilization and route packets accordingly. This is made possible thanks to the use of elastic buffers for control flow, a clever type of handshaking in a way similar to asynchronous circuits. Another prominent feature of R-NoC is that internal routing and arbitration are completely distributed which allows for significant freedom in deciding internal router topology and parameters. This work leverages this property and proposes novel yet unexplored configurations for which an in-depth evaluation of corresponding implementations on 45 nm CMOS technology is given. Each configuration is evaluated performance and power-wise on both synthetic and real application traffic. Several R-NoC configurations are identified and demonstrated to provide very significant performance improvements over standard mesh configurations and a typical input-buffered router, without compromising area and power consumption. Exploiting the distributed nature of R-NoC routers, a diagonally-linked configuration is then proposed which incurs moderate area overhead and features yet better performance and energy efficiency.

Editorial for the Special Issue on Network on Chip (NoC) and Reconfigurable Systems

“…In this Special Issue on Network on Chip (NoC) and Reconfigurable Systems, we include eight papers covering different aspects related to 3D NoC [ 1 , 2 ], GALS NoC [ 3 ], NoC routing [ 4 , 5 , 6 ], application of NoC to the Internet of Things (IoT) [ 7 ], and dynamic partially reconfigurable architectures [ 8 ].…”

“…This work considers the usage of circulant topologies as a promising deadlock-free topology for networks-on-chip (NoCs). In [ 6 ], Effiong et al design an R-NoC (NoC Router) inspired by real-life multi-lane traffic roundabouts and consists of lanes shared by multiple input/output ports to maximize buffering resource utilization. This router is implemented on 45 nm CMOS technology.…”