Combined Impact of BTI and Temperature Effect Inversion on Circuit Performance

Sootkaneung, Warin; Chookaew, Sasithorn; Howimanporn, Suppachai

doi:10.1109/ats.2016.34

Cited by 4 publications

(2 citation statements)

References 24 publications

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“…41 In both planar devices and FinFET devices, the threshold voltage decreases at the higher temperature, and the mobility of charge carriers in the channel decreases due to the ionized impurity and phonon scattering. 42 TEI happens due to the fact that FinFET channels are usually undoped or lightly doped, so they exhibit only a small change in mobility with temperature. It has been shown in Ref.…”

Section: Thermal Effect Inversion (Tei)mentioning

confidence: 99%

“…44 Since thermal issues also emerge as important reliability concerns throughout the system lifetime, the TEI effect can compensate some of the performance degradation introduced by reliability threats such as BTI and EM. 42,45 The optimal operating temperature can be exploited to reduce design cost and runtime operating power for overall cooling with the proper utilization of the TEI effect.…”

Section: Thermal Effect Inversion (Tei)mentioning

confidence: 99%

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Back to the Future: Digital Circuit Design in the FinFET Era

Guo¹,

Verma²,

Gonzalez-Guerrero³

et al. 2017

Journal of Low Power Electronics

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It has been almost a decade since FinFET devices were introduced to full production; they allowed scaling below 20 nm, thus helping to extend Moore's law by a precious decade with another decade likely in the future when scaling to 5 nm and below. Due to superior electrical parameters and unique structure, these 3-D transistors offer significant performance improvements and power reduction compared to planar CMOS devices. As we are entering into the sub-10 nm era, FinFETs have become dominant in most of the high-end products; as the transition from planar to FinFET technologies is still ongoing, it is important for digital circuit designers to understand the challenges and opportunities brought in by the new technology characteristics. In this paper, we study these aspects from the device to the circuit level, and we make detailed comparisons across multiple technology nodes ranging from conventional bulk to advanced planar technology nodes such as Fully Depleted Silicon-on-Insulator (FDSOI), to FinFETs. In the simulations we used both state-of-art industry-standard models for current nodes, and also predictive models for future nodes. Our study shows that besides the performance and power benefits, FinFET devices show significant reduction of short-channel effects and extremely low leakage, and many of the electrical characteristics are close to ideal as in old long-channel technology nodes; FinFETs seem to have put scaling back on track! However, the combination of the new device structures, double/multi-patterning, many more complex rules, and unique thermal/reliability behaviors are creating new technical challenges. Moving forward, FinFETs still offer a bright future and are an indispensable technology for a wide range of applications from high-end performance-critical computing to energy-constraint mobile applications and smart Internet-of-Things (IoT) devices.

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Section: Thermal Effect Inversion (Tei)mentioning

confidence: 99%