Combining Abstract Interpretation with Model Checking for Timing Analysis of Multicore Software

Lv, Mingsong; Yi, Wang; Guan, Nan; Yu, Ge

doi:10.1109/rtss.2010.30

Cited by 83 publications

(67 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Similarly, the PTARM (Liu et al 2012) enforces constant latencies for all instructions, including loads and stores; however, both cases represent customized hardware. Lv et al (2010) used timed automata to model the memory bus and the memory request patterns. Their method handles instruction accesses only and may suffer from state-space explosion when applied to data accesses.…”

Section: Related Work With a Focus On The Memory Busmentioning

confidence: 99%

An extensible framework for multicore response time analysis

et al. 2017

View full text Add to dashboard Cite

In this paper, we introduce a multicore response time analysis (MRTA) framework, which decouples response time analysis from a reliance on contextindependent WCET values. Instead, the analysis formulates response times directly The additional material includes: Section 4: analysis for warmed-up caches and dynamic scratchpads (Sects. 4.3 and 4.2). Section 7: extensions to the task model, including RTOS and interrupts, shared software resources, and open systems and incremental verification. Section 8: presentation of a cycle-accurate multicore simulator. Section 9: evaluation of different local memory types (Sect. 9.2), a comparison between predictable and reference architectures (Sect. 9.3), and a verification of the precision of the analysis using results from the simulator (Sect. 9.4). 123Real-Time Syst from the demands placed on different hardware resources. The MRTA framework is extensible to different multicore architectures, with a variety of arbitration policies for the common interconnects, and different types and arrangements of local memory. We instantiate the framework for single level local data and instruction memories (cache or scratchpads), for a variety of memory bus arbitration policies, including: Round-Robin, FIFO, Fixed-Priority, Processor-Priority, and TDMA, and account for DRAM refreshes. The MRTA framework provides a general approach to timing verification for multicore systems that is parametric in the hardware configuration and so can be used at the architectural design stage to compare the guaranteed levels of real-time performance that can be obtained with different hardware configurations. We use the framework in this way to evaluate the performance of multicore systems with a variety of different architectural components and policies. These results are then used to compose a predictable architecture, which is compared against a reference architecture designed for good average-case behaviour. This comparison shows that the predictable architecture has substantially better guaranteed real-time performance, with the precision of the analysis verified using cycle-accurate simulation.

show abstract

Section: Related Work With a Focus On The Memory Busmentioning

confidence: 99%

An extensible framework for multicore response time analysis

et al. 2017

View full text Add to dashboard Cite

show abstract

“…Lv et al [4] presented an approach based on model-checking (UPPAAL) combined with abstract cache interpretation to estimate WCET of non-sharing code programs on a shared-bus multicore platform. Gustavsson et al [5] moved further and tried to extend the former work [4] concentrating on modeling code sharing programs and enhancing the hardware architecture with additional data cache but without the consideration of bus contentions.…”

Section: Model-checkingmentioning

confidence: 99%

“…Gustavsson et al [5] moved further and tried to extend the former work [4] concentrating on modeling code sharing programs and enhancing the hardware architecture with additional data cache but without the consideration of bus contentions. In their work, they considered general tasks modeled at assembly level and analyzed these when mapped to an architecture where every core has its private L1 cache and all cores share an L2 cache without sharing a bus.…”

Section: Model-checkingmentioning

confidence: 99%

See 1 more Smart Citation

Exploiting Segregation in Bus-Based MPSoCs to Improve Scalability of Model-Checking-Based Performance Analysis for SDFAs

Fakih

Grüttner

Fränzle³

et al. 2013

IFIP Advances in Information and Communication Technology

View full text Add to dashboard Cite

Abstract. The timing predictability of embedded systems with hard real-time requirements is fundamental for guaranteeing their safe usage. With the emergence of multicore platforms this task becomes even more challenging, because of shared processing, communication and memory resources. Model-checking techniques are capable of verifying the performance properties of applications running on these platforms. Unfortunately, these techniques are not scalable when analyzing systems with large number of tasks and processing units. In this paper, a modelchecking based approach that allows to guarantee timing bounds of multiple Synchronous Data Flow Applications (SDFA) running on shared-bus multicore architectures will be extended for a TDMA hypervisor architecture. We will improve the the number of SDFAs being analyzable by our model-checking approach by exploiting the temporal and spatial segregation properties of the TDMA architecture and demonstrate how this method can be applied.

show abstract

“…Li and Malik [11] and Li et al [12] proposed the implicit path enumeration technique (IPET) to compute the worst-case path for deriving the WCET accurately. Recently, the timing analysis has been extended from single-core processors [13][14][15][16][17][18][19] to multicore processors [20][21][22][23][24][25][26][27][28]. A good summary of contributions in the area of WCET analysis can be found in [3].…”

Section: A Wcet Analysis At Jbc Levelmentioning

confidence: 99%

Overview of Real-Time Java Computing

Sun¹,

Zhang²

2013

Journal of Computing Science and Engineering

View full text Add to dashboard Cite

This paper presents a complete survey of recent techniques that are applied in the field of real-time Java computing. It focuses on the issues that are especially important for hard real-time applications, which include time predictable garbage collection, worst-case execution time analysis of Java programs, real-time Java threads scheduling and compiler techniques designed for real-time purpose. It also evaluates experimental frameworks that can be used for researching real-time Java. This overview is expected to help researchers understand the state-of-the-art and advance the research in real-time Java computing.

show abstract

Combining Abstract Interpretation with Model Checking for Timing Analysis of Multicore Software

Cited by 83 publications

References 18 publications

An extensible framework for multicore response time analysis

An extensible framework for multicore response time analysis

Exploiting Segregation in Bus-Based MPSoCs to Improve Scalability of Model-Checking-Based Performance Analysis for SDFAs

Overview of Real-Time Java Computing

Contact Info

Product

Resources

About