Combining ATPG and symbolic simulation for efficient validation of embedded array systems

Parthasarathy, G.; Iyer, M.K.; Feng, Tao; Wang, L.-C.; Cheng, Kwang-Ting; Abadir, Magdy S.

doi:10.1109/test.2002.1041762

Cited by 12 publications

(23 citation statements)

References 22 publications

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“…Three threshold values (8,12, and ∞) are set to see how fast the circuit misbehavior is detected with different signal numbers. To find the final set of signals to observe, GNU Linear Programming Kit (GLPK) 4.32 [7] was used as the ILP solver.…”

Section: Resultsmentioning

confidence: 99%

“…Unlike during pre-silicon verification, the accessibility and visibility of internal signals are very limited in post-silicon debug and hence this is the major challenge in the validation and debug of first silicon. Hence, identifying and resolving problems in ICs after first silicon is a very time consuming and extremely complex task [6], [8], [9], [12]- [14], [17], [20], [22], [23].…”

Section: Introduction and Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Efficient Trace Signal Selection for Silicon Debug by Error Transmission Analysis

Yang

Touba

2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Section: Resultsmentioning

confidence: 99%

Section: Introduction and Related Workmentioning

confidence: 99%

Efficient Trace Signal Selection for Silicon Debug by Error Transmission Analysis

Yang

Touba

2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…The technology for this is already used widely in industry (Pandey and Bryant, 1999;Chen and Bryant, 2001;Jones, 2002;Parthasarathy et al, 2002).…”

Section: Related Workmentioning

confidence: 99%

TLSim and EVC: a term-level symbolic simulator and an efficient decision procedure for the logic of equality with uninterpreted functions and memories

Velev¹,

Bryant²

2005

IJES

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We present a tool flow for high-level design and formal verification of embedded processors. The tool flow consists of the term-level symbolic simulator TLSim, the decision procedure EVC (Equality Validity Checker) for the logic of Equality with Uninterpreted Functions and Memories (EUFM), and any SAT solver. TLSim accepts high-level models of a pipelined implementation processor and its non-pipelined specification, as well as a command file indicating how to simulate them symbolically, and produces an EUFM formula for the correctness of the implementation. EVC exploits the property of Positive Equality and other optimisations in order to translate the EUFM formula to an equivalent Boolean formula that can be solved with any SAT procedure. An earlier version of our tool flow was used to formally verify a model of the M • CORE processor at Motorola, and detected bugs.Keywords: design automation; hardware design languages; logic; microprocessors; simulation; symbolic manipulation.Reference to this paper should be made as follows: Velev, M.N. and Bryant, R.E. (2005) 'TLSim and EVC: a term-level symbolic simulator and an efficient decision procedure for the logic of equality with uninterpreted functions and memories', Int.

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“…Nevertheless, when verifying an operation that involves interactions among multiple array blocks, the OBDD sizes could often blow up. To overcome the problem, our earlier work incorporates an ATPG-style decision procedure into the symbolic simulation framework [7]. In that approach, the symbolic simulation process is partitioned into separate and simpler sub-processes by ATPG assigning constant values to a set of selected control signal lines.…”

Section: Introductionmentioning

confidence: 99%

“…Our current approach is different from the previous approach [7] in terms of three aspects: (1) Instead of explicit partitioning a design into control and datapath, our current approach adopts a partition scheme implicitly in the symbolic simulation process. (2) Instead of using a decision procedure such as ATPG to handle the control part [7], we use symbolic simulation on both the control and the datapath. (3) Instead of utilizing symbolic encoding to minimize OBDD sizes on the datapath, we adopt a simpler node collapsing method that gives the same efficiency.…”

Section: Introductionmentioning

confidence: 99%

Enhanced symbolic simulation for efficient verification of embedded array systems

Feng

Wang

Cheng

et al. 2003

Proceedings of the 2003 Conference on Asia South Pacific Design Automation - ASPDAC

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Abstract-In the past, Symbolic Trajectory Evaluation (STE) was shown to be effective for verifying individual array blocks. However, when applying STE to verify multiple array blocks together as a single system, the run-time OBDD sizes would often blow up. In this paper, we propose using a "dual-rail" symbolic simulation scheme to facilitate the application of STE proof methodology for verifying array systems. The proposed scheme implicitly partitions a given design into control domain and datapath domain, and symbolic simulation is carried out on both domains. With this scheme, the run-time OBDD sizes during the symbolic simulation for each domain can be limited. We demonstrate the effectiveness of our approach by verifying the Memory Management Unit (MMU) in Motorola high-performance microprocessors. The verification of MMU as a whole was not possible before because of the OBDD size blow-up problem when an ordinary symbolic simulator was used in the STE proof process.

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Combining ATPG and symbolic simulation for efficient validation of embedded array systems

Cited by 12 publications

References 22 publications

Efficient Trace Signal Selection for Silicon Debug by Error Transmission Analysis

Efficient Trace Signal Selection for Silicon Debug by Error Transmission Analysis

TLSim and EVC: a term-level symbolic simulator and an efficient decision procedure for the logic of equality with uninterpreted functions and memories

Enhanced symbolic simulation for efficient verification of embedded array systems

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