Combining high productivity and high performance in image processing using Single Assignment C on multi-core CPUs and many-core GPUs

Abstract

In this paper the challenge of parallelization development of industrial high performance inspection systems is addressed concerning a conventional parallelization approach versus an auto-parallelized technique. Therefore, we introduce the functional array processing language Single Assignment C (SaC), which relies on a hardware virtualization concept for automated, parallel machine code generation for multicore CPUs and GPUs. Additional, software engineering aspects like programmability, productivity, understandability, maintainability and resulting achieved gain in performance are discussed from the point of view of a developer. With several illustrative benchmarking examples from the field of image processing and machine learning, the relationship between runtime performance and efficiency of development is analyzed.

SaC/C formulations of the all‐pairs N‐body problem and their performance on SMPs and GPGPUs

“…We conclude that, for the running example of all-pairs N -body simulation, SAC and its tool chain do exhibit the desired combination of high software engineering productivity and high execution performance. These findings are in line with several previous application studies [26][27][28].…”

“…These findings are in line with several previous application studies [26][27][28]. These findings are in line with several previous application studies [26][27][28].…”

A Dataflow IR for Memory Efficient RIPL Compilation to FPGAs

“…There is a need for One data locality approach in data parallel language compilers is to start from an imperative language with loops, and fuse the successive loops over the input image1 into an expression tree in a single loop, to improve cache locality and on chip register locality e.g. [6,12]. For CPU or GPU scheduling, this expression tree can be duplicated to apply the same fused computation on image chunks in a data parallel fashion.…”