Combining low-leakage techniques for FPGA routing design

Abstract

Reconfigurable architectures are well suited for wireless applications since they provide high performance computation together with the capability to adapt to changing communication protocols. Moving to 90nm technology and below, FPGAs could suffer from leakage energy consumption due to the large number of inactive transistors. We propose to combine super cut-off, body biasing and multi-threshold techniques to reduce the leakage current of programmable interconnections, which give by far the main contribution to static power dissipation. Super cut-off (gate biasing) technique is well suited for high-speed pass-transistors, while body biasing can be adopted for large buffers. On the other hand high threshold transistors can be used where delays are not critical. We show the design of SRAM cells generating the required high swing signals for gate-biased and body-biased transistors without affecting transistor reliability. Compared to a standard design the adoption of a mixed technique reduces routing leakage by more than one order of magnitude with only a 5% increase in switch delay and a 9% in tile area, while with respect to a full dual-threshold approach, delay is reduced by 23%.

Device and Architecture Cooptimization for FPGA Power Reduction

“…Region based power gating for FPGA logic blocks [10] and fine-grained power-gating for FPGA interconnects [11] were proposed, and Vdd programmability was applied to both FPGA logic blocks [12], [13] and interconnects [14]- [16]. A new type of routing multiplexer and an input control method were developed [17] to reduce leakage of unused routing multiplexers, and circuitry combining gate biasing, body biasing and multi-threshold techniques was designed [18] to reduce interconnect leakage. Architecture evaluation has been performed first for area and delay.…”

A Dual-Threshold FPGA Routing Design for Subthreshold Leakage Reduction

“…The reason for focusing on the programmable interconnections is that they represent one of the main sources of leakage power in FPGAs [1], [9]. The dual threshold voltage design technique, which is a static approach, has been widely used in ASIC designs for reducing leakage.…”