Combining Prefetch Control and Cache Partitioning to Improve Multicore Performance

Sun, Gongjin; Shen, Junjie; Veidenbaum, Alexander V.

doi:10.1109/ipdps.2019.00103

Cited by 13 publications

(6 citation statements)

References 36 publications

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“…Various interference models in the literature target specific sources of interference within computer systems. Some models concentrate on interference stemming from the main memory [13,14], while others focus on interference generated by cache memory [15,16], and others yet address interference originating from the memory bus [17,18]. Each of these models incorporates the impacts of interference into schedulability analysis, typically focusing on a single shared hardware resource at a time.…”

Section: Related Workmentioning

confidence: 99%

Schedulability Analysis in Fixed-Priority Real-Time Multicore Systems with Contention

Ortiz,

Guasque,

Balbastre

et al. 2024

Applied Sciences

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In the scheduling of hard real-time systems on multicore platforms, significant unpredictability arises from interference caused by shared hardware resources. The objective of this paper is to offer a schedulability analysis for such systems by assuming a general model that introduces interference as a time parameter for each task. The analysis assumes constrained deadlines and is provided for fixed priorities. It is based on worst-case response time analysis, which exists in the literature for monocore systems. We demonstrate that the worst-case response time is an upper bound, and we evaluate our proposal with synthetic loads and execution on a real platform.

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Section: Related Workmentioning

confidence: 99%

Schedulability Analysis in Fixed-Priority Real-Time Multicore Systems with Contention

Ortiz,

Guasque,

Balbastre

et al. 2024

Applied Sciences

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“…The prefetching control policy [16], [17], [22], [33], [34]aims to improve system performance by exploiting the performance advantages of multiple prefetchers. In recent years, various prefetching controllers based on different prefetching control policies have been proposed.…”

Section: Prefetching Control Policymentioning

confidence: 99%

RL-CoPref: A Reinforcement Learning-based Coordinated Prefetching Controller for Multiple Prefetchers

Fang

Cai

et al. 2023

Preprint

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Modern processors employ data prefetchers to alleviate the impact of long memory access latency. However, current prefetchers are designed for specific memory access patterns, which perform poorly on mixed applications with multiple memory access patterns. To address these issues, RL-CoPref, a reinforcement learning (RL)-based coordinated prefetching controller for multiple prefetchers, is proposed in this paper. RL-CoPref takes diverse program context information as the input, learns to maximize cumulative rewards, and evaluates prefetch quality based on prefetch hits/misses and memory bandwidth utilization. It can dynamically adjust the prefetch activation and prefetch degree, enabling multiple prefetchers to complement each other on mixed applications. Our extensive evaluation, utilizing the ChampSim simulator, demonstrates that RL-CoPref can effectively adapt to various workloads and system configurations, optimizing prefetch control. On average, RL-CoPref achieves 76.15% prefetch coverage, having 35.50% IPC improvement, outperforming state-of-the-art individual prefetchers by 5.91%−16.54% and outperforming SBP, a state-of-the-art (non-RL) prefetch controller, by 4.64%.

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“…Sun et al [97] proposed a mechanism to reduce intercore interferences caused by hardware prefetchers on shared cache multicore processors. The execution of the process is divided into two stages: an initial phase where the necessary statistics are compiled to identify the aggressive prefetch applications, and the second stage of resource allocation.…”

Section: ) Proposal Focused On Achieving a Better Performancementioning

confidence: 99%

A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore Platforms

et al. 2022

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This survey reviews the scientific literature on techniques for reducing interference in real-time multicore systems, focusing on the approaches proposed between 2015 and 2020. It also presents proposals that use interference reduction techniques without considering the predictability issue. The survey highlights interference sources and categorizes proposals from the perspective of the shared resource. It covers techniques for reducing contentions in main memory, cache memory, a memory bus, and the integration of interference effects into schedulability analysis. Every section contains an overview of each proposal and an assessment of its advantages and disadvantages.INDEX TERMS Real-time systems, architecture, multicore, timing analysis, schedulability analysis, WCET, co-runner interference.

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Combining Prefetch Control and Cache Partitioning to Improve Multicore Performance

Cited by 13 publications

References 36 publications

Schedulability Analysis in Fixed-Priority Real-Time Multicore Systems with Contention

Schedulability Analysis in Fixed-Priority Real-Time Multicore Systems with Contention

RL-CoPref: A Reinforcement Learning-based Coordinated Prefetching Controller for Multiple Prefetchers

A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore Platforms

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