Combining Prefetch with Instruction Cache Locking in Multitasking Real-Time Systems

Aparicio, Luis; Segarra, Juan; Rodríguez, Carlos Larrinaga; Viñals, Víctor

doi:10.1109/rtcsa.2010.8

Cited by 14 publications

(21 citation statements)

References 15 publications

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“…Also, hardware proposals such as instruction cache locking and prefetch (e.g. [28]) and detailed analysis methods on conventional instruction caches (e.g. [2]) may guarantee to always hit in certain chunks of instructions.…”

Section: Discussion On Matrix Multiplicationmentioning

confidence: 99%

A predictable hardware to exploit temporal reuse in real-time and embedded systems

Tejero

Segarra

Pedro-Zapater

et al. 2015

Journal of Systems Architecture

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Section: Discussion On Matrix Multiplicationmentioning

confidence: 99%

A predictable hardware to exploit temporal reuse in real-time and embedded systems

Tejero

Segarra

Pedro-Zapater

et al. 2015

Journal of Systems Architecture

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“…As the impact of cache locking on energy efficiency has not been reported (to the best of our knowledge), we intend to bridge such gap by implementing techniques like [16] and [2] within our experimental environment. We also intend to generalize our algorithms for handling unlocked data caches.…”

Section: Discussionmentioning

confidence: 99%

“…Those who prescribe cache locking [4,14] (to trade-off performance for predictability) argue that cache-aware WCET analysis [8,21] often neglects the interference between tasks [15]. They prescribe a combination of instruction prefetching and cache locking [16] [2]. Such works, however, target the minimization of WCET as a single objective and do not report the impact on energy efficiency.…”

Section: Prefetching Under Real-time Constraintsmentioning

confidence: 99%

“…Such works, however, target the minimization of WCET as a single objective and do not report the impact on energy efficiency. On the other hand, those who prescribe the accurate prediction [8,21] of cache behavior (during WCET analysis) argue that cache locking may unncecessarily give up performance [2]. Under such assumption, the original cache abstract semantics proposed in [8] was extended in [22] to incorporate the effect of next-N-line prefetching.…”

Section: Prefetching Under Real-time Constraintsmentioning

confidence: 99%

“…One work extended cache abstract semantics to take prefetching into account [22], another exploited it for optimizing the WCET [5], and a recent one combined it with cache locking [2], but their impact on energy efficiency was not evaluated.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Reconciling real-time guarantees and energy efficiency through unlocked-cache prefetching

Wuerges

Santos

2013

Proceedings of the 50th Annual Design Automation Conference

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For real-time tasks, cache behavior must be constrained via cache locking or predicted by WCET analysis. Since the former gives up energy efficiency for predictability, this paper proposes a novel code optimization that reduces the miss rate of unlocked instruction caches and, provenly, does not increase the WCET. We optimized the 37 programs from the Mälardalen WCET benchmark for 36 cache configurations and two technologies. By exploiting software prefetching on top of on-demand fetching, we reduced the memory's contribution to the energy consumption (by 11.2%), to the average case execution time (by 10.2%), and to the WCET (by 17.4%).

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Optimizing a combined WCET-WCEC problem in instruction fetching for real-time systems

Tejero

Segarra

Rodríguez

et al. 2013

Journal of Systems Architecture

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In real-time systems, time is usually so critical that other parameters such as energy consumption are often not even considered. However, optimizing the worst energy consumption case can be a key factor in systems with severe power-supply limitations. In this paper we study several memory architectures using combined time and energy optimization models for real-time multitasking systems. Each task is modeled using Lock-MS, a method to optimize the WCET of a task, with an added set of constraints to model in the same way the WCEC (worst case energy consumption). Our tested hardware components focus on instruction fetching, including a lockable cache, a line buffer and a sequential prefetch buffer. We test a variety of instruction fetch alternatives optimizing time and energy consumption. Our results show that the accuracy of the estimation of the number of context switches in the worst case may affect very much the resulting WCEC (up to 8 times in our experiments) and that optimizing the WCEC may provide similar execution times than optimizing the WCET, with up to 5 times less energy consumption. Additionally optimization functions combining WCET and WCEC with different weights show very interesting WCET-WCEC trade-offs. This confirms that methodologies testing such optimizations at design time could be very helpful to provide a precise system setup .

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Combining Prefetch with Instruction Cache Locking in Multitasking Real-Time Systems

Cited by 14 publications

References 15 publications

A predictable hardware to exploit temporal reuse in real-time and embedded systems

A predictable hardware to exploit temporal reuse in real-time and embedded systems

Reconciling real-time guarantees and energy efficiency through unlocked-cache prefetching

Optimizing a combined WCET-WCEC problem in instruction fetching for real-time systems

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