Combining Simulation and Virtualization through Dynamic Sampling

Falcón, Ayose; Faraboschi, Paolo; Ortega, Daniel

doi:10.1109/ispass.2007.363738

Cited by 29 publications

(15 citation statements)

References 11 publications

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“…The simulation infrastructure is split into two independent parts: a full system simulator for generating L2 miss memory traces and a network simulator for processing these traces. A modified version of the HP Labs' COTSon simulator [11] generates the traces. (COTSon is based on AMD's SimNow simulator infrastructure.)…”

Section: Methodsmentioning

confidence: 99%

Corona: System Implications of Emerging Nanophotonic Technology

Vantrease

Schreiber

Monchiero

et al. 2008

2008 International Symposium on Computer Architecture

429

479

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We expect that many-core microprocessors will push performance per chip from the 10 gigaflop to the 10 teraflop range in the coming decade. To support this increased performance, memory and inter-core bandwidths will also have to scale by orders of magnitude. Pin limitations, the energy cost of electrical signaling, and the non-scalability of chip-length global wires are significant bandwidth impediments. Recent developments in silicon nanophotonic technology have the potential to meet these off-and on-stack bandwidth requirements at acceptable power levels.Corona is a 3D many-core architecture that uses nanophotonic communication for both inter-core communication and off-stack communication to memory or I/O devices. Its peak floating-point performance is 10 teraflops. Dense wavelength division multiplexed optically connected memory modules provide 10 terabyte per second memory bandwidth. A photonic crossbar fully interconnects its 256 low-power multithreaded cores at 20 terabyte per second bandwidth. We have simulated a 1024 thread Corona system running synthetic benchmarks and scaled versions of the SPLASH-2 benchmark suite. We believe that in comparison with an electrically-connected many-core alternative that uses the same on-stack interconnect power, Corona can provide 2 to 6 times more performance on many memoryintensive workloads, while simultaneously reducing power.

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Section: Methodsmentioning

confidence: 99%

Corona: System Implications of Emerging Nanophotonic Technology

Vantrease

Schreiber

Monchiero

et al. 2008

2008 International Symposium on Computer Architecture

429

479

View full text Add to dashboard Cite

show abstract

“…Techniques for sampling simulation have been proposed many times before [2], [9], [10], [11], [3], [17], [18]. The two main techniques are SimPoint [3] and SMARTS [2].…”

Section: B Samplingmentioning

confidence: 99%

“…COTSon combines AMD SimNow [19] (a JIT:ing functional x86 simulator) with a set of performance models for disks, networks, and CPUs. The simulator achieves good performance by using a dynamic sampling strategy [17] that uses online phase detection to exploit phases of execution in the target. Since the functional simulator they use can not warm microarchitectural state, they employ a two-phase warming strategy similar to FSA.…”

Section: B Samplingmentioning

confidence: 99%

Full Speed Ahead: Detailed Architectural Simulation at Near-Native Speed

Sandberg¹,

Nikoleris²,

Carlson³

et al. 2015

2015 IEEE International Symposium on Workload Characterization

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Abstract-Popular microarchitecture simulators are typically several orders of magnitude slower than the systems they simulate. This leads to two problems: First, due to the slow simulation rate, simulation studies are usually limited to the first few billion instructions, which corresponds to less than 10% the execution time of many standard benchmarks. Since such studies only cover a small fraction of the applications, they run the risk of reporting unrepresentative application behavior unless sampling strategies are employed. Second, the high overhead of traditional simulators make them unsuitable for hardware/software co-design studies where rapid turn-around is required.In spite of previous efforts to parallelize simulators, most commonly used full-system simulations remain single threaded. In this paper, we explore a simple and effective way to parallelize sampling full-system simulators. In order to simulate at high speed, we need to be able to efficiently fast-forward between sample points. We demonstrate how hardware virtualization can be used to implement highly efficient fast-forwarding in the standard gem5 simulator and how this enables efficient execution between sample points. This extremely rapid fastforwarding enables us to reach new sample points much quicker than a single sample can be simulated. Together with efficient copying of simulator state, this enables parallel execution of sample simulation. These techniques allow us to implement a highly scalable sampling simulator that exploits sample-level parallelism.We demonstrate how virtualization can be used to fast-forward simulators at 90% of native execution speed on average. Using virtualized fast-forwarding, we demonstrate a parallel sampling simulator that can be used to accurately estimate the IPC of standard workloads with an average error of 2.2% while still reaching an execution rate of 2.0 GIPS (63% of native) on average. We demonstrate that our parallelization strategy scales almost linearly and simulates one core at up to 93% of its native execution rate, 19 000x faster than detailed simulation, while using 8 cores.

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“…COTSon [8] employs SimNow as a front-end and PTLsim as a detailed timing model. It uses sampling to determine when to switch back and forth between SimNow and PTLsim.…”

Section: Related Workmentioning

confidence: 99%