Communication synthesis and HW/SW integration for embedded system design

Gogniat, Guy; Auguin, Michel; Bianco, Luc; Pégatoquet, Alain

doi:10.1145/278241.278296

Cited by 6 publications

(4 citation statements)

References 2 publications

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“…Different methods have been exploited for the communications during the system-level synthesis [23], [24], [25] and design space exploration [26], [27]. Some works only attempt to minimize the transfers [4], [28] between the different groups of tasks, without considering bus contention.…”

Section: Related Workmentioning

confidence: 99%

Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems

Ferrandi

Lanzi

Pilato

et al. 2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

141

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To exploit the power of modern heterogeneous multiprocessor embedded platforms on partitioned applications, the designer usually needs to efficiently map and schedule all the tasks and the communications of the application, respecting the constraints imposed by the target architecture. Since the problem is heavily constrained, common methods used to explore such design space usually fail, obtaining low-quality solutions. In this paper, we propose an ant colony optimization (ACO) heuristic that, given a model of the target architecture and the application, efficiently executes both scheduling and mapping to optimize the application performance. We compare our approach with several other heuristics, including simulated annealing, tabu search, and genetic algorithms, on the performance to reach the optimum value and on the potential to explore the design space. We show that our approach obtains better results than other heuristics by at least 16% on average, despite an overhead in execution time. Finally, we validate the approach by scheduling and mapping a JPEG encoder on a realistic target architecture

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Section: Related Workmentioning

confidence: 99%

Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems

Ferrandi

Lanzi

Pilato

et al. 2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

141

View full text Add to dashboard Cite

show abstract

“…Most of the work has been done in optimizing communication architectures for specific designs. In [7], Gogniat et al describe mechanism for interfacing HW/SW interfaces for co-design of embedded systems. Ortega et.…”

Section: Related Workmentioning

confidence: 99%

Automatic communication refinement for system level design

Abdi

Shin

Gajski

2003

Proceedings of the 40th Annual Design Automation Conference

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This paper presents a methodology and algorithms for automatic communication refinement. The communication refinement task in system-level synthesis transforms abstract data-transfer between components to its actual bus level implementation. The input model of the communication refinement is a set of concurrently executing components, communicating with each other through abstract communication channels. The refined model reflects the actual communication architecture. Choosing a good communication architecture in system level designs requires sufficient exploration through evaluation of various architectures. However, this would not be possible with manually refining the system model for each communication architecture. For one, manual refinement is tedious and errorprone. Secondly, it wastes substantial amount of precious designer time. We solve this problem with automatic model refinement. We also present a set of experimental results to demonstrate how the proposed approach works on a typical system level design.

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“…Most of the work has been done in optimizing communication architectures for specific designs. In [5], Gogniat et al describe mechanism for interfacing HW/SW interfaces for co-design of embedded systems. Ortega et.…”

Section: Related Workmentioning

confidence: 99%