Communications infrastructure generation for modular FPGA reconfiguration

Abstract

Modules that are swapped dynamically at run-time on an FPGA have varying communication needs over time. In order to support this, we aim to generate a wiring infrastructure that caters for the dynamically-changing module interfaces. This, however, imposes a regular structure for laying out modules on a device, which may result in longer inter-module wiring paths as compared to traditional methods where the netlists are flattened. This paper studies placing modules within a structured layout to compare resulting circuit speeds with those obtained by traditional methods. Our results indicate that the difference in critical path delay is high at very low utilisation, but that the overhead is absorbed as the number of modules and interconnection density increases to realistic levels. We conclude that implementing such a wiring infrastructure has manageable overheads while having the added advantage of being amenable to dynamic reconfiguration.

The Effectiveness of Configuration Merging in Point-to-Point Networks for Module-based FPGA Reconfiguration

“…We first determine appropriate slot placements for each module. This problem was addressed in [10], in which placement is performed as a two-step process: the first minimizes the number of wires across any cut, and the second minimizes the total wire length. Our experiments were initially performed using an integer linear program, but we now use recursivebisection and branch-and-bound standard-cell placement techniques.…”

“…We analyzed the impact on the critical path delay of such a layout in [10], concluding that the overheads are acceptable in realistic scenarios, and can even be better than a flattened netlist as wiring becomes more dense.…”

Distributing C# methods and threads over Ethernet-connected FPGAs using Kiwi

“…Cardoso [5] describes a C compiler for a reconfigurable execution platform that has course grain for rapid place and route, similar to [4]. Swapping modules at run-time on a Virtex-4 FPGA was presented in [8] and FPGA companies are increasing support for dynamic reconfiguration, but there are many restrictions remaining, such as a tile bitstream being tied to a fixed absolute X-Y co-ordinate within the device with no API for moving it. An alternative approach would be to follow the example of Wires on Demand [9] which performs light-weight run-time placement and routing.…”

Module Graph Merging and Placement to Reduce Reconfiguration Overheads in Paged FPGA Devices

“…The first sub-problem, module placement, was addressed in [4], and in this paper we propose algorithms to solve the mapping (wire delay estimation) and merging (minimising reconfiguration time) sub-problems.…”

“…We first determine appropriate slot placements for each module. We have addressed this problem in [4], where we performed placement as a two-step process; the first minimises the number of wires across any cut, and the second minimises the total wire length. Our experiments were initially performed using an integer linear program, but we now use recursivebisection and branch-and-bound standard-cell placement techniques.…”