Compact and High Speed Architectures of KASUMI Block Cipher

Yasir, Md.; Wu, Ning; Ali, Zain Anwar; Shaikh, Muhammad Mujtaba; Yahya, Muhammad Rehan; Aamir, Muhammad

doi:10.1007/s11277-018-5606-8

Cited by 10 publications

(3 citation statements)

References 15 publications

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“…The two algorithms resemble in terms of Linear / Differential cryptanalysis, architectural characteristics, and the key requirements; nevertheless, they have several contrasting features / design constraints for round operations. The attacks against MISTY1 and 3gpp standardized KASUMI have identified the weaknesses; however, no serious drawbacks / shortcomings have been found against the full 8-rounds MISTY1 and 3gpp standardized KASUMI output feedback (OFB) and Cipher Block Chaining (CBC) modes [11][12][13][14].…”

Section: Introductionmentioning

confidence: 99%

“…Moreover, the repetitive-loop structure results in a low throughput value of 130.2 Mbps and in-turn the high-power consumption [15][16][17][18][19][20][21][22][23][24][25][26]. Studies on static reconfigurable cryptographic modules have also been proposed for SNOW / ZUC algorithms and AES / KASUMI / SNOW / ZUC algorithms signifying flexible implementations [14,[27][28][29][30][31][32][33][34][35][36].…”

Section: Introductionmentioning

confidence: 99%

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On the dynamic reconfigurable implementations of MISTY1 and KASUMI block ciphers

Jiexian,

Khizar,

Ali

et al. 2023

PLoS ONE

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Novel hardware architectures for dynamic reconfigurable implementation of 64-bit MISTY1 and KASUMI block ciphers are proposed to enhance the performance of cryptographic chips for secure IoT applications. The SRL32 primitive (Reconfigurable Look up Tables—RLUTs) and DPR (Dynamic Partial Reconfiguration) are employed to reconfigure single round MISTY1 / KASUMI algorithms on the run-time. The RLUT based architecture attains dynamic logic functionality without extra hardware resources by internally modifying the LUT contents. The proposed adaptive reconfiguration can be adopted as a productive countermeasure against malicious attacks with the added advantage of less reconfiguration time (RT). On the other hand, the block architecture reconfigures the core hardware by externally uploading the partial bit stream and has significant advantages in terms of low area implementation and power reduction. Implementation was carried out on FPGA, Xilinx Virtex 7. The results showed remarkable results with very low area of 668 / 514 CLB slices consuming 460 / 354 mW for RLUT and DPR architectures respectively. Moreover, the throughput obtained for RLUT architecture was found as 364 Mbps with very less RT of 445 nsec while DPR architecture achieved speed of 176 Mbps with RT of 1.1 msec. The novel architectures outperform the stand-alone existing hardware designs of MISTY1 and KASUMI implementations by adding the dynamic reconfigurability while at the same achieving high performance in terms of area and throughput. Design details of proposed unified architectures and comprehensive analysis is described.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

On the dynamic reconfigurable implementations of MISTY1 and KASUMI block ciphers

Jiexian,

Khizar,

Ali

et al. 2023

PLoS ONE

Self Cite

View full text Add to dashboard Cite

show abstract

“…To meet the requirement of the Internet of ings, cryptographic algorithms are frequently optimized for area reduction and high throughput implementation or to achieve a good tradeoff between throughput and speed [12][13][14][15][16][17][18][19][20][21][22][23][24][25]. For low-area design, reutilization/logic optimization methodologies have been widely adopted thereby implementing s-boxes using combinational logic [12][13][14][15][16][17][18][19][20]. A single-round MISTY1 architecture designed for compact implementation is proposed in [20] consisting of only oddround functions, i.e., 2 × FL functions, 1 × FO function, and 1 × 32 bit XOR.…”

Section: Introductionmentioning

confidence: 99%

Design Space Exploration for High-Speed Implementation of the MISTY1 Block Cipher

Hasan

Khizar

Mahmood

et al. 2021

Mathematical Problems in Engineering

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This paper proposes 2 × unrolled high-speed architectures of the MISTY1 block cipher for wireless applications including sensor networks and image encryption. Design space exploration is carried out for 8-round MISTY1 utilizing dual-edge trigger (DET) and single-edge trigger (SET) pipelines to analyze the tradeoff w.r.t. speed/area. The design is primarily based on the optimized implementation of lookup tables (LUTs) for MISTY1 and its core transformation functions. The LUTs are designed by logically formulating S9/S7 s-boxes and FI and {FO + 32-bit XOR} functions with the fine placement of pipelines. Highly efficient and high-speed MISTY1 architectures are thus obtained and implemented on the field-programmable gate array (FPGA), Virtex-7, XC7VX690T. The high-speed/very high-speed MISTY1 architectures acquire throughput values of 25.2/43 Gbps covering an area of 1331/1509 CLB slices, respectively. The proposed MISTY1 architecture outperforms all previous MISTY1 implementations indicating high speed with low area achieving high efficiency value. The proposed architecture had higher efficiency values than the existing AES and Camellia architectures. This signifies the optimizations made for proposed high-speed MISTY1 architectures.

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A General Method for Accelerating the Kasumi Algorithm on Intel Processors

Bai

2018

2018 IEEE 18th International Conference on Communication Technology (ICCT)

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Compact and High Speed Architectures of KASUMI Block Cipher

Cited by 10 publications

References 15 publications

On the dynamic reconfigurable implementations of MISTY1 and KASUMI block ciphers

On the dynamic reconfigurable implementations of MISTY1 and KASUMI block ciphers

Design Space Exploration for High-Speed Implementation of the MISTY1 Block Cipher

A General Method for Accelerating the Kasumi Algorithm on Intel Processors

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