Compact Bell-Shaped Analog Matching-Cell Module for Digital-Memory-Based Associative Processors

Abstract

A compact analog matching-cell module compatible with integration with digital memories has been developed, aiming at building small-area low-power associative processors. The matching cell utilizes bell-shaped current–voltage (I–V) characteristics to create a primitive function of data correlation. The key feature in the present work is the proposal of a calibration scheme that can mitigate the problem of device mismatch caused by process variations. In addition, the matching cell requires only eight n-channel metal–oxide–semiconductor field-effect transistors (NMOS transistors) to implement, enabling a very compact implementation of a matching-cell array. The proof-of-concept chip was fabricated using 0.35 µm complementary MOS (CMOS) technology, and the concept has been verified by measurement results. A matching time of less than 2.2 µs at the operating frequency of 33.3 MHz has been shown, which is, in principle, independent of the number of template vectors. Furthermore, the current consumption can be made as small as 80 nA per matching cell when the cell is operated in the subthreshold regime. This matching-cell module, therefore, is promising for building low-power and compact pattern-matching systems in combination with high-density digital memory technologies.

Implementing brain-like systems using nano functional devices

“…In Fig. 4(a), resonance elements implemented by CMOS [13][14][15] and NMOS [16,17] circuits are shown along with their measured characteristics. We have already developed associative processors using these resonance circuits [13,14,16,17] and have demonstrated such systems are applicable to robust image recognition [14].…”

“…Such a correlation function can be well implemented using the resonance-type I-V characteristics frequently observed in nono devices. Vast-scale integration of such devices would enable us to establish fine-grain parallel processing on a chip, assuring a real-time response performance of a system even with very small currents driven [15] and NMOS [17] circuits (a) and those obtained form a floating-gate single electron transistor [12]. by nano devices.…”

Low-Power Analog Associative Processors Employing Resonance-Type Current-Voltage Characteristics

“…In this chapter, a compact resonance-characteristics matching cell using only NMOS transistors in order to emulate the resonance-type I-V characteristics of nano devices and to build a small-area low-power associative processor will be described. In addition, a new calibration scheme (Bui & Shibata, 2008a) that can compensate for matching errors due to device mismatch is presented. System configuration of a single-core architecture and the major circuitries utilized in the prototype chip design as well as measurement results are presented in Section 2.…”

“…Moreover, the problem associated with inter-chip communication delay which is critical in the time-domain WTA operation was resolved by a newly-developed winner-code-decision scheme (Bui & Shibata, 2008b;2009). 2. Single-core architecture of analog associative processor 2.1 System architecture Figure 1 shows the block diagram of the single-core associative processor developed in our work (Bui & Shibata, 2008a). It consists of two main parts, the digital memory module and the proposed analog matching-cell module.…”

Explorations in Morphic Architectures

“…However, intelligent sensors have been re-spotlighted, because Information processing Associative memory (CMOS [7], SET [8,9]), data mining and Inference (CMOS) [10], winner takes all selection (CMOS) [11], noise-driven computing (see Table 22.2), locomotion controller (CMOS) [12] Intelligent sensors Vision Edge detection (CMOS [13], SET [14]), motion detection (CMOS [15], SET [16]), stereo vision (CMOS) [17], visual tracking (CMOS) [18], adaptive gain control (CMOS) [19], orientation selection (CMOS) [20], high-speed sensors (CMOS) [21] Others…”